Integrated circuit and semiconductor device

Patent metadata

Field	Value
Publication number	US-9905561-B2
Application number	US-201715409523-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Apr 8, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first gate electrode;
a second gate electrode, the second gate electrode being spaced apart from the first gate electrode in a first side of a first direction;
a third gate electrode spaced apart from and aligned with the second gate electrode in a second direction substantially perpendicular to the first direction;
a fourth gate electrode, the fourth gate electrode being spaced apart from the third gate electrode in a second side of the first direction;
a first contact on the first gate electrode;
a second contact on the second gate electrode;
a third contact on the third gate electrode; and
a fourth contact on the fourth gate electrode,
wherein the first contact and the fourth contact are electrically connected,
wherein the second contact and the third contact are electrically connected, and
wherein the first side of the first direction and the second side of the first direction are opposite from each other.

2. The semiconductor device of claim 1 ,
wherein the first contact and the fourth contact are electrically connected by a first metal layer.

3. The semiconductor device of claim 1 ,
wherein the first gate electrode and the second gate electrode are disposed on a first fin, and the third gate electrode and the fourth gate electrode are disposed on a second fin.

4. The semiconductor device of claim 1 ,
wherein the semiconductor device further includes a first dummy gate electrode, the first gate electrode and the first dummy gate electrode are aligned in the second direction.

5. The semiconductor device of claim 1 ,
wherein the semiconductor device further includes a second dummy gate electrode, the fourth gate electrode and the second dummy gate electrode are aligned in the second direction.

6. The semiconductor device of claim 2 ,
wherein the second contact and the third contact are electrically connected by a second metal layer.

7. The semiconductor device of claim 6 ,
wherein the first metal layer and the second metal layer are different from each other.

8. A semiconductor device comprising:
a first active region extending in a first direction;
a second active region having different conductivity type from the first active region and extending in the first direction;
a first gate electrode extending in a second direction over the first active region; and
a second gate electrode extending in the second direction over the second active region,
wherein the first gate electrode is spaced apart from and aligned with the second gate electrode in the second direction substantially perpendicular to the first direction, and
wherein the first gate electrode and the second gate electrode are electrically connected.

9. The semiconductor device of claim 8 ,
wherein the semiconductor device further comprises a first contact on the first gate electrode and a second contact on the second gate electrode, and
wherein the first gate electrode and the second gate electrode are electrically connected by connecting the first contact and the second contact.

10. The semiconductor device of claim 9 , wherein the first gate electrode is disposed on a first fin and the second gate electrode is disposed on a second fin.

11. The semiconductor device of claim 9 , wherein the first contact and the second contact are electrically connected by a metal layer.

12. The semiconductor device of claim 11 , wherein a portion of the metal layer that connects the first contact and the second contact is aligned in the second direction with the first gate electrode.

13. The semiconductor device of claim 9 , wherein the first contact and the second contact are not disposed both on the first active region and the second active region.

14. A method of creating a layout of a standard cell, comprising:
creating, by a processor according to a program stored in a memory of a computing system, a first gate electrode extending in a first direction over a first active region and a second active region;
cutting, by the processor according to the program, the first gate electrode to generate an upper first gate electrode and a lower first gate electrode; and
connecting, by the processor according to the program, the upper first gate electrode and the lower first gate electrode,
wherein the second active region is spaced apart from and having different conductivity type from the first active region.

15. The method of claim 14 , the method further comprising:
creating, by the processor according to the program, an upper contact on the upper first gate electrode and a lower contact on the lower first gate electrode; and
connecting, by the processor according to the program, the upper contact and the lower contact by a metal layer to connect the upper first gate electrode and the lower first gate electrode.

16. The method of claim 14 , wherein the first gate electrode is disposed on a first fin over the first active region and is disposed on a second fin over the second active region.

17. The method of claim 15 ,
wherein the upper contact and the lower contact are not disposed not both on the first and second active regions.

18. The method of claim 14 , the method further comprising:
creating, by the processor according to the program, a second gate electrode in the first direction over the first active region and the second active region;
creating, by the processor according to the program, a third gate electrode in the first direction over the first active region and the second active region;
cutting, by the processor according to the program, the second gate electrodes to generate an upper second gate electrode and a lower second gate electrode; and
cutting, by the processor according to the program, the third gate electrode to generate an upper third gate electrode and a lower third gate electrode,
wherein the first gate electrode, the second gate electrode and the third gate electrode are cut at the same time.

19. The method of claim 18 , wherein the second gate electrode is spaced apart from the first gate electrode in a second direction substantially perpendicular to the first direction, and the third gate electrode is spaced apart from the first gate electrode in the second direction.

20. The method of claim 19 , the method further comprising:
creating, by the processor according to the program, an upper contact on the upper second gate electrode;
creating, by the processor according to the program, a lower contact on the lower third gate electrode; and
connecting, by the processor according to the program, the upper contact on the upper second gate electrode and the lower contact on the lower third gate electrode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ha Young
• Cho Sung We
• Song Tae Joong
• Baek Sang Hoon

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H01L27/0924 Primary

  Electricity · mapped topic