Integrated circuit

Patent metadata

Field	Value
Publication number	US-9786645-B2
Application number	US-201414297965-A
Country	US
Kind code	B2
Filing date	Jun 6, 2014
Priority date	Nov 6, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

An integrated circuit is provided. A standard cell includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS transistors are disposed in a first row and a second row in the semiconductor substrate. The NMOS transistors are disposed in a third row in the semiconductor substrate. The third row is adjacent to the first and second rows and arranged between the first and second rows.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a standard cell, comprising a plurality of PMOS transistors disposed in a first row and a second row in the semiconductor substrate and a plurality of NMOS transistors disposed in a third row in the semiconductor substrate,
wherein the third row is adjacent to the first and second rows and arranged between the first and second rows,
wherein the NMOS transistors disposed in the third row are adjacent to the PMOS transistors disposed in the first and second rows, and
wherein a width of a gate of the NMOS transistors is longer than a width of a gate of the PMOS transistors.

2. The integrated circuit as claimed in claim 1 , wherein a quantity of the PMOS transistors in the first row is equal to a quantity of the PMOS transistors in the second row.

3. The integrated circuit as claimed in claim 1 , wherein one of the PMOS transistors disposed in the first row, one of the NMOS transistors disposed in the third row and one of the PMOS transistors disposed in the second row share the same gate.

4. An integrated circuit, comprising:
a first standard cell, comprising a plurality of first NMOS transistors disposed in a first row and a second row in a semiconductor substrate and a plurality of first PMOS transistors disposed in a third row in the semiconductor substrate, wherein the third row is adjacent to the first and second rows and arranged between the first and second rows; and
a second standard cell, comprising a plurality of second PMOS transistors disposed in the third row and a fourth row in the semiconductor substrate and a plurality of second NMOS transistors disposed in the second row in the semiconductor substrate, wherein the second row is adjacent to the third and fourth rows and arranged between the third and fourth rows.

5. The integrated circuit as claimed in claim 4 , wherein a width of each gate of the second NMOS transistor in the second row is at least twice a width of each gate of the first NMOS transistors in the first and second rows.

6. The integrated circuit as claimed in claim 4 , wherein a width of a gate of the first PMOS transistor in the third row is at least twice a width of each gate of the second PMOS transistors in the third and fourth rows.

7. The integrated circuit as claimed in claim 4 , wherein half of the first NMOS transistors are disposed in the first row, and the other half of the first NMOS transistors are disposed in the second row and coupled to the half of the first NMOS transistors in the first row via a plurality of individual gates, respectively, wherein the first NMOS transistors in the first and second rows have the same width.

8. The integrated circuit as claimed in claim 4 , wherein half of the second PMOS transistors are disposed in the third row, and the other half of the second PMOS transistors are disposed in the fourth row and coupled to the half of the second PMOS transistors in the third row via a plurality of individual gates, respectively, wherein the second PMOS transistor in the third and fourth rows have the same width.

9. The integrated circuit as claimed in claim 4 , further comprising:
a third standard cell, comprising at least one third PMOS transistor disposed in the third row in the semiconductor substrate and at least one third NMOS transistor disposed in a first area of the second row in the semiconductor substrate.

10. The integrated circuit as claimed in claim 9 , wherein the second NMOS transistors are disposed in a second area of the second row in the semiconductor substrate, and a width of each gate of the second NMOS transistors in the second area of the second row is at least twice a width of a gate of the third NMOS transistor in the first area of the second row.

11. The integrated circuit as claimed in claim 9 , wherein half of the second PMOS transistors are disposed in the third row, wherein a width of a gate of the third PMOS transistors is equal to a width of each gate of the second PMOS transistors in the third row.

12. The integrated circuit as claimed in claim 4 , further comprising:
a fourth standard cell, comprising at least one fourth NMOS transistor disposed in the first row in the semiconductor substrate and at least one fourth PMOS transistor disposed in a third area of the third row in the semiconductor substrate,
wherein a width of each gate of the second NMOS transistor in the second row is at least twice a width of a gate of the fourth NMOS transistor in the first row.

13. The integrated circuit as claimed in claim 12 , wherein half of the second PMOS transistors are disposed in a fourth area of the third row, wherein a width of a gate of the fourth PMOS transistors is equal to a width of each gate of the second PMOS transistors in the third row.

14. An integrated circuit, comprising:
a standard cell, comprising a plurality of NMOS transistors disposed in a first row and a second row in the semiconductor substrate and a plurality of PMOS transistors disposed in a third row in the semiconductor substrate,
wherein the third row is adjacent to the first and second rows and arranged between the first and second rows,
wherein the PMOS transistors disposed in the third row are adjacent to the NMOS transistors disposed in the first and second rows, and
wherein a width of a gate of the PMOS transistors is longer than a width of a gate of the NMOS transistors.

15. The integrated circuit as claimed in claim 14 , wherein a quantity of the NMOS transistors in the first row is equal to a quantity of the NMOS transistors in the second row.

16. The integrated circuit as claimed in claim 14 , wherein one of the NMOS transistors disposed in the first row, one of the PMOS transistors disposed in the third row and one of the NMOS transistors disposed in the second row share the same gate.

Assignees

• Mediatek Inc

Inventors

• Yang Jen-Hang

Classifications

• H01L2027/11874

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L27/11807

  Electricity · mapped topic

• H10D84/974

  Layout specifications, i.e. inner core regions · CPC title

• H10D84/907

  CMOS gate arrays · CPC title