Multi supply cell arrays for low power designs

Patent metadata

Field	Value
Publication number	US-9483600-B2
Application number	US-201514645336-A
Country	US
Kind code	B2
Filing date	Mar 11, 2015
Priority date	Mar 14, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

First claim

What is claimed is:

1. A metal oxide semiconductor (MOS) device, comprising:
a set of standard cells extending in a first direction and including at least two standard cells, the set of standard cells comprising at least a portion of a first n-type well (n-well) coupled to a first voltage source;
a first isolation region adjacent a first side of the set of standard cells in the first direction, the first isolation region including a first n-well tap; and
a second isolation region adjacent a second side of the set of standard cells in the first direction, the second isolation region including a second n-well tap,
wherein the first n-well is isolated from a second n-well adjacent to the first n-well by at least one of the first and second isolation regions, the second n-well being coupled to a second voltage source, and
wherein the set of standard cells further comprising a first subset of standard cells and a second subset of standard cells adjacent the first subset of standard cells in a second direction orthogonal to the first direction, and wherein each standard cell in the set of standard cells comprises a metal 2 (M2) layer interconnect extending across the standard cell in the first direction, M2 layer interconnects of the standard cells in the first subset of standard cells forming a first M2 layer interconnect that extends across the first subset of standard cells in the first direction, M2 layer interconnects of the standard cells in the second subset of standard cells forming a second M2 layer interconnect that extends across the second subset of standard cells in the first direction.

2. The device of claim 1 , wherein the set of standard cells comprises a plurality of standard cells adjacent to each other in the first direction, wherein the plurality of standard cells, the first isolation region, and the second isolation region all have a same height.

3. The device of claim 1 , wherein the first subset of standard cells includes one or more standard cells adjacent to each other in the first direction, the second subset of standard cells includes one or more standard cells adjacent to each other in the first direction, the first isolation region and the second isolation region each have a same height, and standard cells in the first and second subsets of standard cells each have a height approximately half the height of the first and second isolation regions.

4. The device of claim 3 , wherein each of the standard cells in the set of standard cells has an output, each output being at a metal layer lower than a metal 3 (M3) layer.

5. The device of claim 4 , wherein the output of each of the standard cells in the set of standard cells is at a metal 1 (M1) layer.

6. The device of claim 3 , further comprising:
a first set of power interconnects extending across the device in the second direction, the first set of power interconnects being unconnected to the set of standard cells; and
a second set of power interconnects extending across the device in the second direction, the second set of power interconnects being connected to the set of standard cells.

7. The device of claim 6 , wherein the first set of power interconnects has a first pitch and the second set of power interconnects has a second pitch, the first pitch being approximately equal to the second pitch.

8. The device of claim 7 , further comprising a third set of power interconnects extending across the device in the second direction, the third set of power interconnects being unconnected to the set of standard cells, the third set of power interconnects having a third pitch that is approximately equal to the first pitch and the second pitch.

9. The device of claim 8 , wherein each power interconnect in the second set of power interconnects extends in the second direction approximately midway between a power interconnect of the first set of power interconnects and a power interconnect of the third set of power interconnects, wherein a first set of vias respectively coupled to each power interconnect in the first set of power interconnects is aligned in the first direction with a second set of vias respectively coupled to each power interconnect in the second set of power interconnects, and wherein the second set of vias are not configured in one or more unused tracks in a metal 4 (M4) layer.

10. The device of claim 8 , wherein each power interconnect in the first set of power interconnects extends adjacent to a power interconnect in the third set of power interconnects without a power interconnect of the second set of power interconnects therebetween.

11. The device of claim 6 , further comprising:
a second set of standard cells extending in the first direction, the second set of standard cells including at least two standard cells;
a third isolation region adjacent a first side of the second set of standard cells in the first direction, the third isolation region including a third n-well tap; and
a fourth isolation region adjacent a second side of the second set of standard cells in the first direction, the fourth isolation region including a fourth n-well tap,
wherein the second set of standard cells, the third isolation region, and the fourth isolation region are dislocated from the set of standard cells, the first isolation region, the second isolation region.

12. The device of claim 11 , further comprising a fourth set of power interconnects extending across the device in the second direction, the fourth set of power interconnects being connected to the second set of standard cells.

13. The device of claim 12 , wherein power interconnects in the second set of power interconnects and the fourth set of power interconnects extend in the second direction on different tracks.

14. The device of claim 12 , wherein a subset of power interconnects in the second set of power interconnects and the fourth set of power interconnects extend in the second direction on a same set of tracks.

15. The device of claim 1 , wherein the set of standard cells comprises at least one buffer cell.

16. A method of operation of a metal oxide semiconductor (MOS) device, comprising:
flowing a current through a set of standard cells extending in a first direction and including at least two standard cells, the set of standard cells comprising at least a portion of a first n-type well (n-well) coupled to a first voltage source;
flowing a current through a first n-well tap included in a first isolation region, the first isolation region adjacent a first side of the set of standard cells in the first direction; and
flowing a current through a second n-well tap included in a second isolation region adjacent a second side of the set of standard cells in the first direction,
wherein the first n-well is isolated from the second n-well adjacent to the first n-well by at least one of the first and second isolation regions, the second n-well being coupled to a second voltage source, and
wherein the set of standard cells further comprising a first subset of standard cells and a second subset of standard cells adjacent the first subset of standard cells in a second direction orthogonal to the first direction, and wherein each standard cell in the set of standard cells comprises a metal 2 (M2) layer interconnect extending across the standard cell in the first direction, M2 layer interconnects of the standard cells in the first subset of standard cells forming a first M2 layer interconnect that extends across the first subset of standard cells in the first direction, M2 layer interconnects of the standard cells in the second subset of standard cells forming a second M2

Assignees

• Qualcomm Inc

Inventors

• Bansal Mamta
• Doddannagari Uday
• Gupta Paras
• Vilangudipitchai Ramaprasath
• Najdesamii Parissa
• Kumar Dorav
• Partani Nitin

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H04W72/0453

  Resources in frequency domain, e.g. a carrier in FDMA · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title