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US8975712B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975712-B2 |
| Application number | US-201313893524-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 14, 2013 |
| Priority date | May 14, 2013 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
First claim
Opening claim text (preview).
What is claimed: 1. A method, comprising: forming first and second transistor devices in and above adjacent first and second active regions that are separated by an isolation region formed in a semiconductor substrate, said first and second transistors comprising at least one source/drain region and a shared gate structure: forming a continuous conductive line that spans across said isolation region, wherein said continuous conductive line contacts said at least one source/drain…
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Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8975712B2 cover?
- One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the con…
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0193. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).