Fabrication of a vertical fin field effect transistor having a consistent channel width

Patent metadata

Field	Value
Publication number	US-9837405-B1
Application number	US-201615226823-A
Country	US
Kind code	B1
Filing date	Aug 2, 2016
Priority date	Aug 2, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

First claim

What is claimed is:

1. A method of forming a vertical fin field effect transistor having a consistent channel width, comprising:
forming a plurality of vertical fins on a substrate;
oxidizing at least one of the plurality of vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material to form a tapered upper portion, a tapered lower portion and a straight channel portion there between;
removing at least a portion of the oxide to form an oxide spacer on the sidewalk of at least one of the plurality of vertical fins;
introducing a dopant into at least a portion of the substrate between the plurality of vertical fins; and
removing the tapered upper portion of at least one of the plurality of vertical fins.

2. The method of claim 1 , further comprising removing the oxide spacer from the sidewalls of the at least one of the plurality of vertical fins.

3. The method of claim 2 , further comprising forming a gate structure on the at least one of the plurality of vertical fins.

4. The method of claim 1 , wherein the plurality of vertical fins are single crystal silicon.

5. The method of claim 1 , wherein oxidizing the plurality of vertical fin(s) involves a wet oxidation.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title