Doping channels of edge cells to provide uniform programming speed and reduce read disturb

Patent metadata

Field	Value
Publication number	US-9922992-B1
Application number	US-201715483256-A
Country	US
Kind code	B1
Filing date	Apr 10, 2017
Priority date	Apr 10, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.

First claim

What is claimed is:

1. A method for fabricating a memory device, comprising:
etching a set of memory holes in a plurality of word line layers, the plurality of word line layers are vertically spaced apart from one another by dielectric layers in a stack, the set of memory holes are arranged between first and second isolation regions which extend vertically a height of the stack, the set of memory holes comprises memory holes in a first edge region of the stack adjacent to the first isolation region, a second edge region of the stack adjacent to the second isolation region, and an interior region between the first and second edge regions;
depositing a channel layer in the set of memory holes;
masking the memory holes in the interior region; and
while the memory holes in the interior region are masked, doping the channel layers in the memory holes of the first and second edge regions.

2. The method of claim 1 , wherein:
the doping the channel layers in the memory holes of the first and second edge regions comprises depositing a doped spin on glass over the memory holes of the first and second edge regions and heating the doped spin on glass to cause dopant to diffuse from the spin on glass into the memory holes of the first and second edge regions and into the channel layers in the memory holes of the first and second edge regions.

3. The method of claim 1 , wherein:
the doping the channel layers in the memory holes of the first and second edge regions comprises depositing a doped solid over the memory holes of the first and second edge regions and heating the doped solid to cause dopant to diffuse from the solid into the memory holes of the first and second edge regions and into the channel layers in the memory holes of the first and second edge regions.

4. The method of claim 1 , wherein:
the doping comprises supplying an n-type dopant to the channel layers in the memory holes of the first and second edge regions using plasma doping.

5. The method of claim 1 , wherein:
the doping the channel layers in the memory holes of the first and second edge regions comprises supplying a carrier gas enriched with an n-type dopant to the memory holes of the first and second edge regions.

6. The method of claim 1 , wherein:
the memory holes in the set of memory holes have equal widths.

7. The method of claim 1 , wherein:
the doping comprises supplying an n-type dopant to the channel layers in the memory holes of the first and second edge regions.

8. The method of claim 1 , wherein:
the plurality of word lines layers are separate from one another by dielectric layers in a stack;
the plurality of word lines layers are formed by etching away nitride layers in the stack by supplying an etchant to the first edge region and the second edge region before the interior region, thereby forming voids in the stack between the dielectric layers, and subsequently supplying a metal in the voids.

9. The method of claim 8 , further comprising:
depositing a blocking oxide layer in the set of memory holes before the depositing of the channel layer, the supplying of the etchant to the first edge region and the second edge region before the interior region results in the blocking oxide layer of the memory holes of the first and second edge regions becoming thinner than the blocking oxide layer of the memory holes of the interior region.

Assignees

• Sandisk Technologies Llc

Inventors

• Yu Xuehong
• Dong Yingda

Classifications

• H10P32/141

  the applied layer comprising oxides only · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P50/283

  by chemical means · CPC title