Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels

Patent metadata

Field	Value
Publication number	US-10068657-B1
Application number	US-201715430299-A
Country	US
Kind code	B1
Filing date	Feb 10, 2017
Priority date	Feb 10, 2017
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

First claim

We claim:

1. An apparatus, comprising:
a plurality of blocks of memory cells, wherein in each block, the memory cells are arranged in vertical NAND strings in a plurality of sub-blocks, wherein each block comprises conductive layers spaced apart vertically, the conductive layers spaced apart vertically comprise word lines connected to the memory cells, the plurality of sub-blocks are arranged in a row on a substrate, each sub-block is elongated and has a length in a first direction and a width in a second direction perpendicular to the first direction, and perpendicular to a direction in which the vertical NAND strings extend, the row extends in the second direction, and the widths vary along the row; and
a control circuit configured with a voltage ramping period for each sub-block which is a function of the width of the sub-block, wherein the voltage ramping period is for a voltage applied to at least one of the conductive layers.

2. The apparatus of claim 1 , wherein:
each sub-block comprises separate word lines; and
the voltage ramping period is for the separate word lines in each sub-block.

3. The apparatus of claim 1 , wherein:
sets of adjacent sub-blocks comprises shared word lines; and
the voltage ramping period is for the shared word lines in each set of adjacent sub-blocks.

4. The apparatus of claim 1 , wherein:
the voltage ramping period is for a selected word line connected to selected memory cells; and
the voltage ramping period occurs in a sensing operation for the selected memory cells and comprises a period between (a) a time when the voltage begins to ramp to a demarcation level on the selected word line and (b) a time when sensing is performed for the selected memory cells relative to the demarcation level.

5. The apparatus of claim 1 , wherein:
each NAND string comprises a drain end select gate transistor;
in each sub-block, one of the conductive layers comprises a select gate line connected to the drain end select gate transistors; and
the voltage ramping period is for the select gate line.

6. The apparatus of claim 5 , wherein:
the voltage ramping period occurs in a program loop and comprises a period between (a) a time when the voltage begins to ramp down on the select gate line to cause the drain end select gate transistors to begin to transition from a conductive state to a non-conductive state and (b) a time when a pass voltage begins to ramp up on the word lines.

7. The apparatus of claim 1 , wherein:
the voltage ramping period is a function of a repeating pattern of the widths along the row.

8. The apparatus of claim 1 , wherein:
the voltage ramping period is alternatingly relatively larger and relatively smaller along the row when the widths are alternatingly narrower and wider, respectively.

9. The apparatus of claim 1 , wherein:
the voltage ramping period increases progressively along the row as the widths decrease progressively across the row.

10. The apparatus of claim 1 , wherein:
the voltage ramping period varies with the widths.

11. The apparatus of claim 1 , wherein:
the voltage ramping period is progressively greater and then progressively smaller across the row of sub-blocks as the widths are progressively smaller and then progressively greater, respectively, across the row of sub-blocks.

12. The apparatus of claim 1 , wherein:
the sub-blocks are separated by isolation areas;
each sub-block comprises a row of the vertical NAND strings extending in the first direction; and
a distance between the row of the vertical NAND strings and an adjacent isolation area varies among the sub-blocks.

13. A method for configuring a memory device, comprising:
performing programming operations for selected sub-blocks of a plurality of sub-blocks of memory cells, wherein the plurality of sub-blocks are arranged in a row on a substrate and widths of the plurality of sub-blocks vary in a direction in which the row extends, the memory cells are arranged in vertical NAND strings, each vertical NAND string comprises a drain end select gate transistor, each sub-block comprises conductive layers spaced apart vertically including word lines connected to the memory cells and a select gate line connected to the drain end select gate transistors, and an allowable voltage ramp down period on the select gate line for unselected sub-blocks of the plurality of sub-blocks before a ramp up of voltages on unselected word lines among the word lines connected to the memory cells is set to be different in each of the programming operations;
for each of the selected sub-blocks, performing a read operation after each programming operation, obtaining a count of a number of read errors, and determining a shortest value of the voltage ramping period for which the count of read errors is below a threshold;
determining a pattern in the shortest value for the selected sub-blocks relative to positions of the selected sub-blocks in the row, wherein the pattern in the shortest value corresponds to a pattern in the widths of the plurality of sub-blocks; and
configuring a control circuit for use in a subsequent operation involving another sub-block of the plurality of sub-blocks with a voltage ramping period, wherein the configuring is based on the pattern in the shortest value and a position of the another sub-block in the row.

14. The method of claim 13 , wherein:
the subsequent operation comprises a sensing operation for selected memory cells connected to a selected word line in the another sub-block; and
the voltage ramping period comprises a period between (a) a time when a voltage begins to ramp to a demarcation level on the selected word line and (b) a time when sensing is performed for the selected memory cells relative to the demarcation level.

15. The method of claim 13 , wherein:
in each unselected sub-block, the allowable voltage ramp down period comprises a period between (a) a time when a voltage begins to ramp down on the select gate line to cause the drain end select gate transistors to begin to transition from a conductive state to a non-conductive state and (b) a time when a pass voltage begins to ramp up on the unselected word lines.

16. The method of claim 13 , wherein:
the subsequent operation comprises a programming operation for selected memory cells connected to a selected word line in the another sub-block; and
the voltage ramping period comprises a period between (a) a time when a voltage begins to ramp down on a select gate line in the another sub-block to cause drain end select gate transistors in the another sub-block to begin to transition from a conductive state to a non-conductive state and (b) a time when a pass voltage begins to ramp up on unselected word lines in the another sub-block.

17. The method of claim 13 , wherein:
the pattern in the shortest value indicates that the shortest value is alternatingly higher and lower along the row; and
the voltage ramping period is configured to be alternatingly higher and lower along the row.

18. The method of claim 13 , wherein:
the pattern in the shortest value indicates that the shortest value is progressively larger along the row; and
the voltage ramping period is configured to be progressively larger along the row.

19. An apparatus, comprising:
a row of sub-blocks of memory cells on a substrate, each sub-block is elongated and has a length in a first direction and a width in a second direction perpendicular to the first direction, and the row extends in the second direction;
means for initiating a sensing operation f

Assignees

• Sandisk Technologies Llc

Inventors

• Yu Xuehong
• Pang Liang
• Dong Yingda

Classifications

• G11C16/107

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C2029/1202

  Word line control · CPC title