Adaptive determination of program parameter using program of erase rate

Patent metadata

Field	Value
Publication number	US-9852800-B2
Application number	US-201615062661-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Mar 7, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.

First claim

We claim:

1. An apparatus, comprising:
a set of memory cells in a block;
sense circuits connected to the set of memory cells;
a driver connected to the set of memory cells; and
a control circuit, the control circuit configured to:
cause the driver to apply a set of pulses to the set of memory cells,
cause the sense circuits to evaluate a characteristic of the set of memory cells, the characteristic comprises threshold voltage, current or resistance;
based on results from the sense circuits, determine a rate of change of the characteristic,
set an adjustable programming parameter based on the rate of change of the characteristic, and

program memory cells in the block using the adjustable programming parameter, wherein:
the block is a multi-layer memory block comprising sub-blocks;
memory cells of the multi-layer memory block are arranged along memory holes which extend vertically in the multi-layer memory block;
diameters of the memory holes vary along a height of the multi-layer memory block;
the set of memory cells is arranged in one layer in one of the sub-blocks; and
the adjustable programming parameter is used in programming of sets of memory cells in the one layer in another of the sub-blocks.

2. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to one or more levels in an erase operation.

3. The apparatus of claim 1 , wherein:
the adjustable programming parameter comprises an adjusted step size;
the set of memory cells is connected to a word line; and
the programming of memory cells in the block using the adjustable programming parameter involves the set of memory cells connected to the word line and occurs in a single programming pass in which the pulses are stepped up by an initial step size and then by the adjusted step size.

4. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to a set of levels; and
the control circuit is configured to determine the rate of change of the characteristic based on counts of the pulses used to cause the characteristic to reach each level of the set of levels, and based on a slope of a straight line fit of data points, wherein each data point comprises one of the levels and a corresponding one of the counts of the pulses.

5. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to one or more levels; and
the control circuit configured to determine for one of the pulses a number of memory cells of the set of memory cells which exceeds a level of the one or more levels and if the number exceeds a threshold, increase the level by a delta and cause the sense circuits to compare the characteristic of the set of memory cells to the level plus the delta.

6. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to a set of levels; and
the control circuit is configured to determine the rate of change of the characteristic based on a slope of a straight line fit of data points, each data point comprising one of the levels of the set of levels and a corresponding one of the pulses.

7. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to one or more levels in a programming operation; and
the control circuit is configured to determine when to cause the sense circuits to compare the characteristic to the one or more levels based on a programming progress of the set of memory cells during the programming operation.

8. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to one or more verify levels in a programming operation; and
the control circuit is configured to:
during the set of pulses, lockout some memory cells of the set of memory cells from further programming while continuing programming of other memory cells of the set of memory cells; and
determine the rate of change of the characteristic based on results from the sense circuits for the other memory cells and not based on results from the sense circuits for the locked out memory cells.

9. The apparatus of claim 1 , wherein:
the sense circuits are configured to evaluate the characteristic of the set of memory cells relative to one or more levels in a programming operation; and
the control circuit is configured to erase the set of memory cells to a first depth prior to determining the rate of change of the characteristic and to a second depth, higher than the first depth, after the determining the rate of change of the characteristic and prior to the programming of memory cells in the block using the adjustable programming parameter.

10. The apparatus of claim 1 , wherein:
the control circuit is configured to detect that an ambient temperature is outside of a specified range and determine the rate of change of the characteristic in response to the detection.

11. The apparatus of claim 1 , wherein:
the control circuit is configured to detect a number of program-verify iterations used in programming the set of memory cells and determine the rate of change of the characteristic in response to the detection.

12. The apparatus of claim 1 , wherein:
the adjustable programming parameter is used in programming sets of memory cells in an adjacent layer in each of the sub-blocks, the adjacent layer is adjacent to the one layer.

13. The apparatus of claim 1 , wherein:
the adjustable programming parameter comprises an adjusted step size.

14. A method, comprising:
applying a set of program voltages to a set of memory cells in a single programming pass, wherein the program voltages increase according to an initial step size, and the set of memory cells is in a block;
determining counts of the program voltages used in programming the memory cells to different target data states having different verify levels in the single programming pass;
determining an adjustable programming parameter based on a rate of change of the counts; and
performing subsequent programming of memory cells in the block using the adjustable programming parameter.

15. The method of claim 14 , wherein:
determining a slope of a straight line fit of data points, each data point comprising one of the different verify levels and a corresponding one of the counts of the program voltage; and
determining the adjustable programming parameter based on a ratio of a target slope to the determined slope.

16. The method of claim 14 , wherein:
each memory cell in the set of memory cells is programmed to a highest verify level of the different verify levels.

17. The method of claim 14 , wherein:
multiple verify voltages are applied after one of the program voltages; and
a highest verify voltage of the multiple verify voltages is used to obtain one of the counts.

18. The method of claim 14 , wherein:
the counts comprise a count of the program voltages used in programming the memory cells to one target data state having one verify level and a count of the program voltages used in programming the memory cells to another target data state having another verify level which is higher than the one verify level.

19. An apparatus, comprising:
means for applying program voltages in respective program loops to a set of memory cells in a p

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Lang Murong
• Dutta Deepanshu
• Hsu Cynthia

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title