Coincident memory bank access via cross connected shared bank resources

Patent metadata

Field	Value
Publication number	US-11024361-B2
Application number	US-201715400507-A
Country	US
Kind code	B2
Filing date	Jan 6, 2017
Priority date	Jan 6, 2017
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

First claim

What is claimed is:

1. A memory device with coincident memory bank access, the memory device comprising:
a first bank having a first set of bitlines for accessing a first set of rows in a first memory cell array; each of the first set of bitlines being connected by one cross-connect switch located within the first bank to a first sense amplifier, the first sense amplifier being positioned within the first bank and coupled to a first row buffer;
a second bank having a second set of bitlines for accessing a second set of rows in a second memory cell array; each of the second set of bitlines being connected by one cross-connect switch located within the second bank to a second sense amplifier, the second sense amplifier being positioned within the second bank and coupled to a second row buffer;
the first sense amplifier being selectively connected to each bitline of the second set of bitlines of the second bank by a pair a cross-connect switches, where each pair of cross-connect switches is formed by one cross-connect switch within the first bank coupled to one cross-connect switch of the second bank by a circuit trace; the second sense amplifier being selectively connected to each bitline of the first set of bitlines of the first bank by a respective pair of the cross-connect switches;
a first bank arbitrator coupled to each cross-connect switch of the first bank with a separate circuit trace, the first bank arbitrator controls each cross-connect switch of the first bank via one or more bank select signals; and
a second bank arbitrator coupled to each cross-connect switch of the second bank with a separate circuit trace, the second bank arbitrator controls each cross-connect switch of the second bank via one or more bank select signals.

2. The memory device of claim 1 , wherein at least one of the first and second bank arbitrators configures one or more cross-connect switches to sequence a first row operation and a second row operation to the first bank.

3. The memory device of claim 2 , wherein the first row operation is performed by selectively connecting the first sense amplifier to the first set of bitlines via the one or more cross-connect switches, and the second row operation is performed by selectively connecting the second sense amplifier to the first set of bitlines via the one or more cross-connect switches.

4. The memory device of claim 3 , wherein the first row operation comprises one of a refresh operation and a row activation operation, and the second row operation comprises the other of the refresh operation and the row activation operation.

5. The memory device of claim 1 , wherein the first bank and the first sense amplifier are disposed in a first plane, and the second bank and the second sense amplifier are disposed in a second plane.

6. The memory device of claim 1 , wherein the first and second banks form a dynamic random access memory (DRAM), and the first memory cell array and the second memory cell array are subarrays within the DRAM.

7. A memory device with coincident memory bank access, the memory device comprising:
means for storing data in a first memory cell array accessed via a first set of bitlines; each of the first set of bitlines being connected by one cross-connect switch located within the first means for storing to a first sense amplifier, the first sense amplifier being positioned within the means for storing data in the first memory cell array and coupled to a first row buffer;
means for storing data in a second memory cell array accessed via a second set of bitlines; each of the second set of bitlines being connected by one cross-connect switch located within the second means for storing to a second sense amplifier, the second sense amplifier being positioned within the means for storing data in the second memory cell array and coupled to a second row buffer;
means for selectively connecting the first sense amplifier to each bitline of the second set of bitlines of the second means for storing by using a pair a cross-connect switches, where each pair of cross-connect switches is formed by one cross-connect switch within the first means for storing coupled to one cross-connect switch of the second means for storing by a circuit trace; the means for selectively connecting also selectively connecting the second sense amplifier to each bitline of the first set of bitlines of the first means for storing by a respective pair of the cross-connect switches; and
the means for selectively connecting comprising first and second arbitrator modules coupled to each pair of cross-connect switches, the first arbitrator module being coupled to a respective cross-connect switch within the first means for storing by a circuit trace, the second arbitrator module being coupled to a respective cross-connect switch within the second means for storing by a circuit trace, each arbitrator module controlling a respective cross-connect switch within a bank via one or more memory cell select signals.

8. The memory device of claim 7 , further comprising:
means for generating a refresh operation to one or more banks when a refresh timeline is approaching.

9. The memory device of claim 7 , further comprising:
means for sequencing a first row operation and a second row operation to the first bank.

10. The memory device of claim 9 , wherein the first row operation is performed by selectively connecting the first sense amplifier to the first set of bitlines via one or more of the cross-connect switches, and the second row operation is performed by selectively connecting the second sense amplifier to the first set of bitlines via one or more of the cross-connect switches.

11. The memory device of claim 10 , wherein the first row operation comprises one of a refresh operation and a row activation operation, and the second row operation comprises the other of the refresh operation and the row activation operation.

12. The memory device of claim 7 , wherein the means for storing data in the first memory cell array and the second memory cell array form a dynamic random access memory (DRAM) subarrays.

Assignees

• Qualcomm Inc

Inventors

• Li Yanru
• Chun Dexter
• Suh Jungwon

Classifications

• G11C8/12 Primary

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C11/40603

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/408 Primary

  Address circuits · CPC title