Using memory protection data
US-12572699-B2 · Mar 10, 2026 · US
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Li Yanru patents
Li Yanru is listed as an inventor on 102 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Li Yanru |
| Total patents | 102 |
| First publication | Jan 29, 2015 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Image Difference Generation
US-2025182336-A1 · Jun 5, 2025 · US
Using Memory Protection Data
US-2024232438-A9 · Jul 11, 2024 · US
Using Memory Protection Data
US-2024135042-A1 · Apr 25, 2024 · US
Dynamic prioritization of system-on-chip interconnect traffic using information from an operating system and hardware
US-11886910-B2 · Jan 30, 2024 · US
Methods and apparatus for in-memory device access control
US-11636231-B2 · Apr 25, 2023 · US
Partial refresh technique to save memory refresh power
US-11631450-B2 · Apr 18, 2023 · US
Protected data streaming between memories
US-11630723-B2 · Apr 18, 2023 · US
Access control for protection of in-memory computation
US-2022269439-A1 · Aug 25, 2022 · US
Protected data streaming between memories
US-2022222137-A1 · Jul 14, 2022 · US
Recent patents
Latest publications not already listed above.
Methods And Apparatus For In-Memory Device Access Control
US-2022027520-A1 · Jan 27, 2022 · US
Partial refresh technique to save memory refresh power
US-2021343331-A1 · Nov 4, 2021 · US
Partial refresh technique to save memory refresh power
US-11164618-B2 · Nov 2, 2021 · US
Bypassing cache memory in a write transaction in a system with multi-level memory
US-11144467-B2 · Oct 12, 2021 · US
Boot time determination of calibration parameters for a component coupled to a system-on-chip
US-11126586-B2 · Sep 21, 2021 · US
Dynamic prioritization of system-on-chip interconnect traffic using information from an operating system and hardware
US-2021200579-A1 · Jul 1, 2021 · US
Coincident memory bank access via cross connected shared bank resources
US-11024361-B2 · Jun 1, 2021 · US
Adaptive power management of dynamic random access memory
US-10956057-B2 · Mar 23, 2021 · US
Selective volatile memory refresh via memory-side data valid indication
US-10878880-B2 · Dec 29, 2020 · US
Read-with-invalidate modified data in a cache line in a cache memory
US-10831658-B2 · Nov 10, 2020 · US
Preemptive decompression scheduling for a NAND storage device
US-10817224-B2 · Oct 27, 2020 · US
Partial refresh technique to save memory refresh power
US-2020321051-A1 · Oct 8, 2020 · US
Write access control for double data rate write-x/datacopy0 commands
US-10795830-B2 · Oct 6, 2020 · US
System and method for booting within a heterogeneous memory environment
US-10783252-B2 · Sep 22, 2020 · US
Boot time determination of calibration parameters for a component coupled to a system-on-chip
US-2020257650-A1 · Aug 13, 2020 · US
Partial refresh technique to save memory refresh power
US-10726904-B2 · Jul 28, 2020 · US
Boot time determination of calibration parameters for a component coupled to a system-on-chip
US-10642781-B2 · May 5, 2020 · US
Selective volatile memory refresh via memory-side data valid indication
US-2020098420-A1 · Mar 26, 2020 · US
Selectable boot CPU
US-10599442-B2 · Mar 24, 2020 · US
Memory access management for low-power use cases of a system on chip via secure non-volatile random access memory
US-10591975-B2 · Mar 17, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 92 |
| Intel Corp | 6 |
| Google Llc | 4 |
| Chun Candace Sachi | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 39 |
| G06F1/3275 | 22 |
| G06F2212/1028 | 15 |
| G06F12/0246 | 15 |
| G06F3/0625 | 13 |