Semiconductor storage device and control method thereof

Patent metadata

Field	Value
Publication number	US-9256523-B2
Application number	US-201214006296-A
Country	US
Kind code	B2
Filing date	Feb 28, 2012
Priority date	Mar 23, 2011
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A memory includes a cell array including memory cells storing data, and a write driver writing data to the cells. A write driver performs or does not perform writing of write data according to write mask data input along with the write data. A multiplexer selectively outputs a write protect signal or the write mask data. The write protect signal is fixed to a command prohibiting the write data from being written. The command is included in the write mask data. A write protect controller controls the multiplexer to output the write protect signal when an address of a write protect area in the cell array matches an address of the write data. The write protect controller controls the multiplexer to output the write mask data as it is when the address of the write protect area in the cell array does not match the address of the write data.

First claim

The invention claimed is:

1. A semiconductor storage device comprising:
a memory cell array including a plurality of memory cells storing data;
a write driver writing data to the memory cell array, the write driver performing, or not performing, writing of write data according to write mask data input along with the write data;
a multiplexer selectively outputting either a write protect signal or the write mask data, the write protect signal being a signal fixed to a command prohibiting the write data from being written, the command being included in the write mask data; and
a write protect controller controlling the multiplexer so as to output the write protect signal when an address of a write protect area in the memory cell array matches an address of the write data, the write protect controller controlling the multiplexer so as to output the write mask data as it is when the address of the write protect area does not match the address of the write data.

2. The device of claim 1 , further comprising a write protect register storing the address of the write protect area.

3. The device of claim 2 , wherein the write protect register is formed by a memory capable of rewriting the address of the write protect area.

4. The device of claim 1 , further comprising a write protect switch designating the address of the write protect area.

5. The device of claim 4 , wherein the write protect switch is formed by a memory capable of rewriting the address of the write protect area.

6. The device of claim 4 , wherein the write protect switch is a physical switch.

7. The device of claim 1 , wherein the device is a nonvolatile memory including a DDR interface.

8. The device of claim 5 , further comprising a write-protect-area designation pin receiving the address of the write protect area.

9. The device of claim 1 , wherein the address of the write protect area is set for a page, for a memory cell array or for a memory chip, the page being a write data unit, or a read data unit.

10. The device of claim 2 , wherein the address of the write protect area is set for a page, for a memory cell array or for a memory chip, the page being a write data unit, or a read data unit.

11. The device of claim 4 , wherein the address of the write protect area is set for a page, for a memory cell array or for a memory chip, the page being a write data unit, or a read data unit.

12. The device of claim 1 , further comprising a write mask data port to which the write mask data is input.

13. A control method for a semiconductor storage device including a memory cell array including a plurality of memory cells storing data, a write driver writing data to the memory cell array according to write mask data input along with write data, and a multiplexer selectively outputting either a write protect signal or the write mask data, the write protect signal being a signal fixed to first write mask data prohibiting the write data from being written, the first write mask data being included in the write mask data, the method comprising:
inputting the write mask data along with the write data;
outputting the write protect signal from the multiplexer to the write driver when an address of a write protect area in the memory cell array matches an address of the write data; and
outputting the write mask data from the multiplexer when the address of the write protect area does not match the address of the write data.

14. The method of claim 13 , wherein the semiconductor storage device is a nonvolatile memory including a DDR interface.

15. A control method for a semiconductor storage device comprising a memory cell array including a plurality of memory cells storing data, the method comprising:
inputting write mask data and write data;
selecting a write protect signal fixed to first write mask data prohibiting the write data from being written, the first write mask data being included in the write mask data when an address of a write protect area in the memory cell array matches an address of the write data; and
selecting the write mask data when the address of the write protect area does not match the address of the write data.

16. The method of claim 15 , wherein the address of the write protect area is set for a page, for a memory cell array or for a memory chip, the page being a write data unit, or a read data unit.

17. The method of claim 15 , wherein the semiconductor storage device is a nonvolatile memory including a DDR interface.

18. A control method for a semiconductor storage device including a memory cell array including a plurality of memory cells storing data, the method comprising:
inputting write data; and
adding a write protect signal to the write data, the write protect signal being fixed to first write mask data prohibiting the write data from being written when an address of a write protect area in the memory cell array matches an address of the write data.

19. The method of claim 18 , wherein the address of the write protect area is set for a page, for a memory cell array or for a memory chip, the page being a write data unit, or a read data unit.

20. The method of claim 18 , wherein the semiconductor storage device is a nonvolatile memory including a DDR interface.

Assignees

• Takizawa Ryousuke
• Toshiba Kk

Inventors

• Takizawa Ryousuke

Classifications

• G11C7/1009 Primary

  Data masking during input/output · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G06F12/1441

  for a range · CPC title

• G06F12/1416

  by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights (G06F12/1458 takes precedence) · CPC title