Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array

Patent metadata

Field	Value
Publication number	US-9779798-B1
Application number	US-201715400515-A
Country	US
Kind code	B1
Filing date	Jan 6, 2017
Priority date	Jan 6, 2017
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

First claim

What is claimed is:

1. A method for providing row tamper protection in a multi-bank memory cell array, the method comprising:
monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array;
in response to monitoring the row activation activity, storing a row activation counter table comprising a plurality of row address entries, each row address entry having a corresponding row activation counter; and
in response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering:
determining the corresponding row address entry associated with the row activation counter exceeding the threshold; and
performing a refresh operation on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

2. The method of claim 1 , further comprising:
determining a new row activation associated with one of the plurality of row address entries; and
incrementing the corresponding row activation counter stored in the row activation counter table.

3. The method of claim 1 , further comprising:
after performing the refresh operation, resetting the row activation counters associated with the one or more adjacent rows.

4. The method of claim 1 , further comprising:
after performing the refresh operation, clearing the row address entries in the row activation counter table corresponding to the one or more adjacent rows.

5. The method of claim 1 , wherein the detecting the one of the plurality of row activation counters has exceeded the threshold occurs comprising:
receiving a new row activation request.

6. The method of claim 5 , wherein the new row activation request is received during a read or write request.

7. A system for providing row tamper protection in a multi-bank memory cell array, the system comprising:
means for monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array;
means for storing a row activation counter table in response to monitoring the row activation activity, the row activation counter comprising a plurality of row address entries, each row address entry having a corresponding row activation counter; and
means for detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering;
means for determining the corresponding row address entry associated with the row activation counter exceeding the threshold; and
means for performing a refresh operation on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

8. The system of claim 7 , further comprising:
means for determining a new row activation associated with one of the plurality of row address entries; and
means for incrementing the corresponding row activation counter stored in the row activation counter table.

9. The system of claim 7 , further comprising:
means for resetting the row activation counters associated with the one or more adjacent rows after performing the refresh operation.

10. The system of claim 7 , further comprising:
means for clearing the row address entries in the row activation counter table corresponding to the one or more adjacent rows after performing the refresh operation.

11. The system of claim 7 , wherein the means for detecting the one of the plurality of row activation counters has exceeded the threshold occurs comprises:
means for receiving a new row activation request.

12. The system of claim 11 , wherein the new row activation request is received during a read or write request.

13. A computer program embodied in a memory and executable by a processor for implementing a method for providing row tamper protection in a multi-bank memory cell array, the method comprising
monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array;
in response to monitoring the row activation activity, storing a row activation counter table comprising a plurality of row address entries, each row address entry having a corresponding row activation counter; and
in response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering:
determining the corresponding row address entry associated with the row activation counter exceeding the threshold; and
performing a refresh operation on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

14. The computer program of claim 13 , wherein the method further comprises:
determining a new row activation associated with one of the plurality of row address entries; and
incrementing the corresponding row activation counter stored in the row activation counter table.

15. The computer program of claim 13 , wherein the method further comprises:
after performing the refresh operation, resetting the row activation counters associated with the one or more adjacent rows.

16. The computer program of claim 13 , wherein the method further comprises:
after performing the refresh operation, clearing the row address entries in the row activation counter table corresponding to the one or more adjacent rows.

17. The computer program of claim 13 , wherein the detecting the one of the plurality of row activation counters has exceeded the threshold occurs comprises:
receiving a new row activation request.

18. The computer program of claim 17 , wherein the new row activation request is received during a read or write request.

19. A system for providing row tamper protection in a multi-bank memory cell array, the system comprising:
a multi-bank memory cell array; and
a row access monitor configured to monitor row activation activity for each of a plurality of banks in the multi-bank memory cell array, the row access monitor comprising logic configured to:
store a row activation counter table comprising a plurality of row address entries, each row address entry having a corresponding row activation counter; and
detect one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering:
determine the corresponding row address entry associated with the row activation counter exceeding the threshold; and
perform a refresh operation on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

20. The system of claim 19 , wherein the row access monitor further comprises logic configured to:
determine a new row activation associated with one of the plurality of row address entries; and
increment the corresponding row activation counter stored in the row activation counter table.

21. The system of claim 19 , wherein the row access monitor further comprises logic configured to:
reset the row activation counters associated with the one or more adjacent rows after performing the refresh operation.

22. The system of claim 19 , wherein the row access monitor further comprises logic configured to:
clear the row address entries in the row activation counter table corresponding to the one or more adjacent rows after performing the refresh operation.

23. The system of claim 19 , wherein the logic configured to detect the one of the plurality of row activation counters has exceeded the threshold occurs comprises logic configured to:
receive a new row activation request.

24. The syste

Assignees

• Qualcomm Inc

Inventors

• Li Yanru
• Chun Dexter
• Suh Jungwon
• Gantman Alexander

Classifications

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C8/12 Primary

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/40603

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title