Memory refresh method and devices

Patent metadata

Field	Value
Publication number	US-9286965-B2
Application number	US-201113990363-A
Country	US
Kind code	B2
Filing date	Nov 11, 2011
Priority date	Dec 3, 2010
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

First claim

What is claimed is:

1. An integrated circuit device that controls a memory device, the integrated circuit device comprising:
a circuit configured to:
receive an activate command and a data access command; and
responsive to receiving the activate command and the data access command, provide:
a bank address, wherein the bank address identifies a bank of a plurality of banks in a memory device;
a first row address that identifies a first row within the bank of the memory device for a memory access; and
a second row address that identifies a second row within the bank of the memory device to perform a refresh operation; and

a command interface coupled to the circuit, the command interface configured to output the bank address, the first row address, and the second row address provided by the circuit to the memory device, wherein the first row address and the second row address are simultaneously output to the memory device.

2. The integrated circuit device of claim 1 , wherein the first row address identifies the first row within a first memory portion of the bank and the second row address identifies the second row within a second memory portion of the bank.

3. The integrated circuit device of claim 1 , wherein the first row address identifies the first row that is included in one of a first, second, third, and fourth memory portions of the bank, and the second row address identifies the second row that is included in a remaining one other than said one of the first, second, third, and fourth memory portions of the bank.

4. The integrated circuit device of claim 1 , wherein the circuit further provides a third row address that identifies a third row within the bank of the memory device to perform a refresh operation and the interface outputs the third row address to the memory device while the memory device is not being accessed.

5. The integrated circuit device of claim 4 , wherein:
the circuit provides the second row address during a first refresh interval; and
the circuit provides the third row address during a second refresh interval subsequent to the first refresh interval.

6. The integrated circuit device of claim 5 , wherein the third row identified by the third row address is not refreshed during the first refresh interval.

7. A memory module comprising:
a memory device including a plurality of banks, each bank of the plurality of banks having a plurality of storage cells;
a circuit configured to:
receive an activate command and a data access command; and
responsive to receiving the activate command and the data access command, provide:
a bank address, wherein the bank address identifies a bank of the plurality of banks;
a first row address that identifies a first row of memory cells within the bank for a memory access; and
a second row address that identifies a second row of memory cells within the bank to perform a refresh operation;

a command interface coupled to the circuit, the command interface configured to output the bank address, the first row address, and the second row address provided by the circuit;
a data interface coupled between the plurality of the banks and the command interface, the data interface configured to receive the bank address, the first row address, and the second row address from the command interface;
a first plurality of sense amplifiers to sense, in response to the bank address and the first row address, the first row of memory cells in the bank; and
a second plurality of sense amplifiers to refresh the second row of memory cells in the bank based on the second row address, wherein the second plurality of sense amplifiers refreshes the second row of memory cells concurrently with the first plurality of sense amplifiers sensing the first row of memory cells.

8. The memory module of claim 7 , wherein
the circuit generates a second activate command specifying the second row address.

9. The memory module of claim 8 , wherein the circuit generates a third activate command specifying a third row address of memory cells to refresh responsive to receiving the activate command.

10. The memory module of claim 8 , wherein the activate command addresses the first row of memory cells that is included in one of a first, second, third, and fourth memory portions of the bank, and the second activate command addresses the second row of memory cells that is included in a remaining one other than said one of the first, second, third, and fourth memory portions of the bank.

11. The memory module of claim 7 ,
wherein the first row of memory cells is included in a first memory portion of the bank and the second row of memory cells is included a second memory portion of the bank.

12. The memory module of claim 11 , further comprising:
a first row decoder coupled to the first memory portion and to activate the first row of memory cells based on the first row address; and
a second row decoder coupled to the second memory portion and to activate the second row of memory cells based on the second row address.

13. The memory module of claim 12 , wherein the first row decoder and the second row decoder comprise full row decoders.

14. The memory module of claim 7 , wherein the first row of memory cells in the bank and the second row of memory cells in the bank are portions of a single row of memory cells of the bank.

15. A method of operation in a memory module comprising a memory device including a plurality of banks, the method comprising:
receiving an activate command and a data access command;
responsive to receiving the activate command and the data access command, determining a bank address that identifies a bank of the plurality of banks, a first row address that identifies a first row of memory cells within the bank for a memory access, and a second row address that identifies a second row of memory cells within the bank to perform a refresh operation;
sensing, by a first plurality of sense amplifiers included in the memory module, a first row of memory cells in the bank based on the bank address and the first row address; and
refreshing, by a second plurality of sense amplifiers included in the memory module, a second row of memory cells in the bank concurrently with the first row of memory cells being sensed by the first plurality of sense amplifiers, the second row of memory cells refreshed based on the bank address and the second row address.

16. The method of claim 15 , further comprising:
receiving a first activate command specifying a first memory address associated with the first row of memory cells; and
generating a second activate command specifying a second memory address associated with the second row of memory cells responsive to receiving the first activate command.

17. The method of claim 15 , further comprising:
refreshing a third row of memory cells in the predetermined bank while data from memory cells in the predetermined bank are not being accessed.

Assignees

• Perego Richard
• Vogelsang Thomas
• Brooks John
• Rambus Inc

Inventors

• Perego Richard
• Vogelsang Thomas
• Brooks John

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title

• G11C11/408

  Address circuits · CPC title