Shared row buffer system for asymmetric memory

Patent metadata

Field	Value
Publication number	US-9959205-B2
Application number	US-201514710770-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	May 13, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.

First claim

We claim:

1. An electronic memory comprising:
a first memory bank storing data in logical first rows to be accessible through at least one row buffer;
a second memory bank storing data in logical second rows to be accessible through at least one row buffer wherein the first memory bank has a higher data capacity and larger access latency than the second memory bank;
a set of at least two row buffers; and
a set of electrically operable switches between each row buffer and the first memory bank and second memory bank, the electrically operable switches configured so that a given row buffer can exchange data with the first memory bank or in the alternative with the second memory bank according to activation of the electrically operable switches so that each row buffer may transfer data within the electronic memory between the first memory bank and the second memory bank.

2. The electronic memory of claim 1 wherein the set of electrically operable switches are configured so that at least two row buffers may be accessed by either the first memory bank or second memory bank according to activation of the electrically operable switches.

3. The electronic memory of claim 1 further including a memory control system communicating with the electrically operable switches to change a relative number of row buffers communicating with the first memory bank compared to the second memory bank and providing electrical signals.

4. The electronic memory of claim 3 wherein the memory control system provides a dynamic profiling of execution of processes on an electronic computer accessing the electronic memory and changes the relative number of row buffers according to that profiling to improve cumulative execution speed of the processes.

5. The electronic memory of claim 1 further including a writable row assignment table communicating with the electrically operable switches so that each row buffer communicates at any given time with only one of the first and second memory banks and with a specific one of the first and second memory banks determined by data in the row assignment table.

6. The electronic memory of claim 1 further including a writable page table translating a received memory address into a row of one of the first memory bank and second memory bank according to settings of the page table.

7. The electronic memory of claim 6 wherein the page table is held in the first memory bank.

8. The electronic memory of claim 1 further including a memory control system moving data from a given row in the second memory bank to a given row in the first memory bank by:
(a) controlling the electrically operable switches to connect a given row of the second memory bank to a given row buffer;
(b) moving data of the given row of the second memory bank into the given row buffer;
(c) controlling the electrically operable switches to connect the given row buffer to the given row of the first memory bank; and
(d) moving data of the given row buffer to the given row in the first memory bank.

9. The electronic memory of claim 8 wherein the memory control system further moves data from the given row in the first memory bank to the given row in the second memory bank concurrently with steps (a)-(d) by:
(e) controlling the electrically operable switches to connect the given row of the first memory bank to a second given row buffer;
(f) moving data of the given row of the first memory bank into the second given row buffer;
(g) controlling the electrically operable switches to connect the second given row buffer to the given row of the second memory bank; and
(h) moving data of the second given row buffer to the given row in the second memory bank.

10. The electronic memory of claim 9 wherein the memory control system monitors access of rows of the second memory bank to move data from the second memory bank when an access rate of a given row rises above a threshold value.

11. The electronic memory of claim 9 wherein steps (c), (d), (g), and (h) are performed only when new data must be loaded into the given row buffers.

12. The electronic memory of claim 9 wherein each of the row buffers are associated with a dirty bit indicating that contents of the row buffer have been changed since loading from the first memory bank or the second memory bank and wherein steps (c), (d), (g), and (h) are performed by setting dirty bits of corresponding given row buffers.

13. The electronic memory of claim 9 wherein the given row of the first memory bank and the given row of the second memory bank have identical row numbers.

14. The electronic memory of claim 1 wherein each of the rows of the first and second memory banks are mapped to disjoint logical addresses.

15. The electronic memory of claim 1 wherein the first and second memory banks are on a common integrated circuit substrate employing architectures fabricatable in parallel.

16. The electronic memory of claim 1 wherein the first memory and second memory exchange data from memory cells of each logical row with a corresponding bit of a row buffer and wherein the first memory stores multiple bits per each memory cell and the second memory cell stores at least one bit in each memory cell and less than a number of multiple bits in each memory cell of the first memory.

17. The electronic memory of claim 16 wherein the first and second memory banks are resistive memories and storing data as variations in resistance of a material of a data cell.

18. The electronic memory of claim 17 wherein the first and second memory are phase change memories changing a resistance of the material of the data cell by a phase change process.

19. The electronic memory of claim 1 wherein the set of electrically operable switches between each row buffer and the first memory bank and the second memory bank also allow each row buffer to be switched between a read path and write path of the first and second memories respectively.

20. The electronic memory of claim 1 further including an interface adapted for communication between each row buffers and at least one external processor; and
wherein each row buffer may transfer data between the first memory bank and the second memory bank or between a memory bank and the external processor via the interface.

Assignees

• Wisconsin Alumni Res Found

Inventors

• Wang Hao
• Kim Nam Sung

Classifications

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C13/0021

  Auxiliary circuits · CPC title