Structure and method for interconnection with self-alignment

Patent metadata

Field	Value
Publication number	US-11004740-B2
Application number	US-201916560717-A
Country	US
Kind code	B2
Filing date	Sep 4, 2019
Priority date	Sep 27, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

First claim

What is claimed is:

1. A method of forming an integrated circuit structure, comprising:
depositing a first metal layer on a semiconductor substrate;
forming a hard mask on the first metal layer;
patterning the first metal layer to form first metal features using the hard mask as an etch mask;
depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features;
performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask;
removing the hard mask, thereby having portions of the dielectric layer extruded above the first metal features;
forming an inter-layer dielectric (ILD) layer of a second dielectric material different from the first dielectric material; and
patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the dielectric layer.

2. The method of claim 1 , further comprising forming second metal features in the openings of the ILD layer, wherein the second metal features are landing on the first metal features.

3. The method of claim 2 , wherein the ILD layer includes a low-k dielectric material and the dielectric material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, metal oxynitride and a combination thereof.

4. The method of claim 2 , wherein the performing of the CMP process includes recessing both the dielectric layer and the hard mask such that a bottom portion of the hard mask remains.

5. The method of claim 4 , wherein the forming of the hard mask on the first metal layer includes
depositing a metal-containing hard mask; and
patterning the metal-containing hard mask using a lithography process and etching.

6. The method of claim 5 , wherein the metal-containing hard mask includes one of titanium nitride and tungsten-doped carbon (WdC).

7. The method of claim 1 , wherein the depositing of the first metal layer on the semiconductor substrate includes depositing one of molybdenum (Mo), tungsten (W), and ruthenium (Ru).

8. The method of claim 1 , wherein the patterning the ILD layer includes performing an etching process using an etchant containing fluorocarbon radicals and oxygen to selectively etch the ILD layer relative to the dielectric layer.

9. The method of claim 1 , wherein the patterning of the first metal layer to form first metal features includes using a spacer patterning process.

10. The method of claim 1 , wherein the patterning the ILD layer to form openings includes patterning the ILD layer to form trenches and vias by a dual damascene process.

11. The method of claim 2 , wherein
the first metal features are contacts landing on transistors; and
the second metal features include metal lines.

12. The method of claim 2 , wherein
the first metal features are vias; and
the second metal features include metal lines.

13. A method of forming an integrated circuit structure, comprising:
depositing a first metal layer on a semiconductor substrate;
forming a hard mask on the first metal layer;
patterning the first metal layer to form first metal features using the hard mask as an etch mask;
depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features;
recessing evenly both the dielectric layer and the hard mask;
removing the hard mask, thereby having portions of the dielectric layer extruded above the first metal features;
forming an inter-layer dielectric (ILD) layer of a second dielectric material different from the first dielectric material;
patterning the ILD layer to form openings that expose the first metal features; and
forming second metal features in the openings of the ILD layer, wherein the second metal features are constrained to be self-aligned with the first metal features by the extruded portions of the dielectric layer and are landing on the first metal features.

14. The method of claim 13 , wherein the ILD layer includes a low-k dielectric material and the dielectric material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, metal oxy nitride and a combination thereof.

15. The method of claim 13 , wherein the recessing evenly both the dielectric layer and the hard mask includes recessing both the dielectric layer and the hard mask such that a bottom portion of the hard mask remains and a thickness of the remained hard mask is greater than 10 Angstrom.

16. The method of claim 13 , wherein the hard mask includes one of titanium nitride and tungsten-doped carbon (WdC).

17. The method of claim 13 , wherein the patterning the ILD layer includes performing an etching process using an etchant containing fluorocarbon radicals and oxygen to selectively etch the second dielectric material and substantially not etch the first dielectric material.

18. A method of forming an integrated circuit structure, comprising:
depositing a first metal layer on a semiconductor substrate;
depositing a hard mask layer on the first metal layer;
forming a first mandrel material layer on the hard mask layer;
forming a spacer layer on sidewalls of the first mandrel material layer;
forming a second mandrel material layer to fill in gaps defined by the spacer layer and the first mandrel material layer;
performing an etching process to selectively remove the spacer layer, thereby forming first openings defined by the first and second mandrel material layers;
transferring the first openings to the hard mask layer, thereby forming a patterned hard mask;
patterning the first metal layer to form first metal features using the patterned hard mask as an etch mask;
depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features;
recessing evenly both the dielectric layer and the patterned hard mask;
removing the patterned hard mask, thereby having portions of the dielectric layer extruded above the first metal features;
forming an inter-layer dielectric (ILD) layer of a second dielectric material different from the first dielectric material; and
patterning the ILD layer by selective etching to form second openings that expose the first metal features, wherein the second openings are constrained to be self-aligned with the first metal features by the extruded portions of the dielectric layer.

19. The method of claim 18 , further comprising forming second metal features in the second openings of the ILD layer, wherein the second metal features are landing on the first metal features.

20. The method of claim 18 , wherein the recessing evenly both the dielectric layer and the patterned hard mask includes recessing both the dielectric layer and the patterned hard mask such that a bottom portion of the patterned hard mask remains on the first metal features.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semicondctor Mfg Co Ltd

Inventors

• Yang Tai-I
• Liao Yu-Chieh
• Wu Chia-Tien
• Chen Hsin-Ping
• Chen Hai-Ching
• Shue Shau-Lin

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title