Methods of operating memory devices based on sub-block positions and related memory system

Patent metadata

Field	Value
Publication number	US-10971235-B2
Application number	US-202016840290-A
Country	US
Kind code	B2
Filing date	Apr 3, 2020
Priority date	Sep 5, 2017
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

First claim

What is claimed:

1. A method of operating a memory device including a memory block having at least two sub-blocks, the memory block connected to a plurality of ground select lines configured to control coupling to a common source line and connected to a plurality of string select lines configured to control coupling to a plurality of bit lines, the method comprising:
receiving a program command from outside the memory device;
determining if a plurality of selected word lines configured to activate memory cells responsive to the program command are included in a first sub-block or are included in a second sub-block to provide a selected program sub-block;
performing a program operation using a first sequence of a plurality of first selected word lines extending in a first direction from the plurality of ground select lines toward the plurality of string select lines responsive to determining that the plurality of selected word lines are included in the first sub-block; and
performing the program operation using a second sequence of a plurality of second selected word lines extending in a second direction from the plurality of string select lines toward the plurality of ground select lines responsive to determining that the plurality of selected word lines are included in the second sub-block,
wherein the first and second sub-blocks are configured to be classified based on a position of a first reference word line of the at least two sub-blocks during the program operation, and
wherein the first reference word line is included in the plurality of first or second selected word lines.

2. The method of claim 1 , wherein the selected program sub-block is adjacent to the plurality of string select lines, and
wherein performing the program operation comprises performing the program operation using the first sequence of the plurality of first selected word lines in the first direction.

3. The method of claim 1 , wherein the selected program sub-block is adjacent to the plurality of ground select lines, and
wherein performing the program operation comprises performing the program operation using the second sequence of the plurality of second selected word lines in the second direction.

4. The method of claim 1 , further comprising:
performing a precharge operation associated with the program operation using a first precharge path or a second precharge path determined based on a position of a selected precharge sub-block of the first and second sub-blocks connected to the plurality of selected word lines,
wherein the first precharge path is through the plurality of bit lines and the second precharge path is through the common source line,
wherein the first and second sub-blocks are configured to be classified based on a position of a second reference word line of the at least two sub-blocks during the precharge operation, and
wherein the second reference word line is included in the plurality of first or second selected word lines.

5. The method of claim 4 , further comprising:
performing the precharge operation via the first precharge path when the selected precharge sub-block connected to the plurality of selected word lines is adjacent to the plurality of string select lines.

6. The method of claim 5 , wherein the performing of the precharge operation via the first precharge path includes:
disabling a plurality of ground select transistors connected to the plurality of ground select lines;
enabling a plurality of string select transistors connected to the plurality of sting select lines; and
applying a precharge voltage to the plurality of bit lines.

7. The method of claim 4 , further comprising:
performing the precharge operation via the second precharge path when the selected precharge sub-block connected to the plurality of selected word lines is adjacent to the plurality of ground select lines.

8. The method of claim 7 , wherein the performing of the precharge operation via the second precharge path includes:
disabling a plurality of string select transistors connected to the plurality of sting select lines;
enabling a plurality of ground select transistors connected to the plurality of ground select lines; and
applying a precharge voltage to the common source line.

9. The method of claim 1 , further comprising:
performing a respective partial erase operation in the first and second sub-blocks.

10. A method of operating a memory device, the memory device comprising a memory block connected between a common source line and a plurality of bit lines, connected to a plurality of ground select lines configured to control coupling to the common source line, and connected to a plurality of string select lines configured to control coupling to the plurality of bit lines and the memory block comprising at least three sub-blocks, the method comprising:
receiving a command and an address from outside the memory device;
comparing a position of a sub-block connected to a plurality of selected word lines corresponding to the received address with a first reference position of a sub-block for determining a sequence direction of a program operation;
performing, in response to the command, the program operation on target memory cells connected to the plurality of selected word lines by selecting any one of a first sequence direction from the plurality of ground select lines toward the plurality of string select lines and a second sequence direction from the plurality of string select lines toward the plurality of ground select lines, based on the result of the comparison with the first reference position; and
performing a read operation on memory cells connected to a reference word line of the at least three sub-blocks,
wherein a position of a sub-block including the reference word line is used as the first reference position.

11. The method of claim 10 , further comprising:
comparing the position of a sub-block connected to the plurality of selected word lines corresponding to the received address with a second reference position of a sub-block for determining a precharge path; and
performing, in response to the command, a precharge operation on the memory block by selecting any one of a first precharge path through the plurality of bit lines and a second precharge path through the common source line, based on a result of the comparison with the second reference position.

12. The method of claim 11 , wherein a selected sequence direction of the program operation is different from a selected direction of the precharge path.

13. The method of claim 11 , wherein the at least three sub-blocks comprise a first sub-block, a second sub-block, and a third sub-block which are sequentially positioned in a direction from the plurality of bit lines toward the common source line, and
wherein, when the plurality of selected word lines corresponding to the received address are connected to the second sub-block, the performing of the precharge operation on the memory block occurs by selecting the second precharge path, and the performing of the program operation on the target memory cells occurs by selecting the first sequence direction.

14. The method of claim 11 , wherein a selected sequence direction of the program operation is the same as a selected direction of the precharge path.

15. A memory system comprising:
a memory device including a memory block including first and second sub-blocks, each of the first and second sub-blocks including a plurality of memory cells, the first and second sub-blocks connected to a plurality of ground select lines configured to control connection to a common source line, and t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Se-Hwan
• Kim Wan-Dong

Classifications

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title