Non-volatile memory device and method of programming the same

Patent metadata

Field	Value
Publication number	US-9691472-B2
Application number	US-201615067620-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Mar 13, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and connected to n word lines, wherein n is an integer greater than or equal to 3. The method includes programming memory cells of second to n−1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially performed from the second to n−1-th word lines in an order in which the word lines are disposed; and programming memory cells of the first word line to a single level state after the programming memory cells of the second to n−1-th word lines to a multi-level state.

First claim

What is claimed is:

1. A method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and that are connected to n word lines, wherein n is an integer greater than or equal to 3, the method comprising:
programming memory cells of second to n−1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially finished from the second to n−1-th word lines in an order in which the word lines are disposed; and
programming memory cells of the first word line to a single level state after the programming memory cells of the second to n−1-th word lines to a multi-level state.

2. The method of claim 1 , wherein the plurality of memory cells comprise a first region including the memory cells of the second to n−1-th word lines and a second region including the memory cells of the first word line,
wherein the first region is a multi-level cell region configured to store data having at least 2 bits per memory cell, and the second region is a single-level cell region configured to store 1-bit data per memory cell.

3. The memory of claim 1 , wherein the memory cells of the first word line are adjacent to a ground selection transistor, and memory cells of the n-th word line are adjacent to a string selection transistor.

4. The method of claim 3 , wherein a dummy memory cell is disposed in at least one of portions between the memory cells of the first word line and the ground selection transistor, and portions between the memory cells of the n-th word line and the string selection transistor.

5. The method of claim 1 , further comprising programming memory cells of the n-th word line to a single level state after the programming of the memory cells of the second to n−1-th word lines to a multi-level state.

6. The method of claim 1 , wherein a maximum value of threshold voltages of the memory cells of the first word line is lower than or equal to a maximum value of threshold voltages of the memory cells of the second word line.

7. The method of claim 1 , wherein during a program operation, a second pass voltage applied to the first word line is lower than a first pass voltage applied to at least one of the second to n−1-th word lines.

8. The method of claim 1 , wherein during a program operation, a maximum value of a second program voltage applied to the first word line is lower than a maximum value of a first program voltage applied to the second to n−1-th word lines.

9. The method of claim 1 , wherein the non-volatile memory device comprises a plurality of planes that are selected by different string selection lines and that share the first to n-th word lines therebetween,
wherein after memory cells of different planes connected to one word line are sequentially programmed in units of planes, memory cells connected to another word line are programmed.

10. The method of claim 1 , wherein in a memory cell string including the memory cells of the first to n-th word lines, the memory cells of the first word line are programmed last.

Assignees

• Kang Dong-Ku
• Samsung Electronics Co Ltd

Inventors

• Kang Dong-Ku

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C2211/5648

  Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title