Memory performance evaluation using address mapping information
US-2024394164-A1 · Nov 28, 2024 · US
Update block programming order
US9104556B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104556-B2 |
| Application number | US-201414286262-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2014 |
| Priority date | Nov 21, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time.
First claim
Opening claim text (preview).
It is claimed: 1. A method of operating a three-dimensional block-erasable nonvolatile memory formed in a plurality of physical levels of memory cells disposed above a substrate comprising: maintaining a plurality of Single Level Cell (SLC) erase blocks to receive nonsequential data updates of host data; maintaining a plurality of Multi Level Cell (MLC) erase blocks as update blocks that are available to store newly-received sequential data updates of host data for particular ho…
Assignees
Inventors
Classifications
Physics · mapped topic
- G06F12/0246Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9104556B2 cover?
- Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less …
- Who is the assignee on this patent?
- Sandisk Technologies Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).