Program verify word line ramping delay for lower current consumption mode
US-2024395343-A1 · Nov 28, 2024 · US
US8976584B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976584-B2 |
| Application number | US-201313767535-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2013 |
| Priority date | Apr 17, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively.
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What is claimed is: 1. A flash memory device, comprising: a plurality of memory cells formed in a direction perpendicular to a substrate; a first sub word line connected to first memory cells from among the plurality of memory cells, the first sub word line being formed at a first level and selectable using a first selection line; a second sub word line connected to second memory cells from among the plurality of memory cells, the second sub word line being formed at the first…
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