Storage device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9583201-B1
Application number	US-201615017876-A
Country	US
Kind code	B1
Filing date	Feb 8, 2016
Priority date	Sep 7, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A storage device includes a main block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation, a read operation or an erase operation on the sub-blocks, and a control logic configured to control the peripheral circuit so that the erase operation of the sub-blocks is performed in a reverse order to an order of the program operation.

First claim

What is claimed is:

1. A storage device, comprising:
a main block including a plurality of sub-blocks;
a peripheral circuit configured to perform a program operation, a read operation or an erase operation on the sub-blocks; and
a control logic configured to control the peripheral circuit so that the erase operation of the sub-blocks is performed in a reverse direction to a direction of the program operation.

2. The storage device of claim 1 , wherein memory cells included in the main block are grouped in sub-block units.

3. The storage device of claim 1 , wherein the control logic controls the peripheral circuit so that the program operation is performed in page units in the main block and the erase operation is performed in sub-block units.

4. The storage device of claim 1 , wherein the control logic controls the peripheral circuit so that when the program operation of the main block is performed in a direction from a drain selection line to a source selection line, the erase operation is performed on the sub-blocks in a direction from a sub-block adjacent to the source selection line to a sub-block adjacent to the drain selection line, and
the control logic controls the peripheral circuit so that when the program operation of the main block is performed in a direction from the source selection line to the drain selection line, the erase operation is performed in a direction from the sub-block adjacent to the drain selection line to the sub-block adjacent to the source selection line.

5. A method of operating a storage device, the method comprising:
programming sub-blocks included in a selected main block; and
erasing the sub-blocks in a reverse direction to a direction of programming of the sub-blocks.

6. The method of claim 5 , wherein in the programming of the sub-blocks, the sub-blocks are sequentially or randomly selected, and programmed.

7. The method of claim 5 , wherein the programming of the sub-blocks is performed in page units included in the sub-blocks, and
the erasing of the sub-blocks is performed in sub-block.

8. The method of claim 5 , wherein the erasing of the sub-blocks comprises:
determining an erased/programmed state of a selected sub-block; and
erasing the sub-blocks or determining an erased/programmed state of a next sub-block according to a result of a determination.

9. The method of claim 8 , further comprising performing an erase operation in a direction from the selected sub-block in a reverse order to the programming of the sub-blocks when, as the result of the determination, it is determined that the selected sub-block is in the program state.

10. The method of claim 8 , further comprising determining the erased/programmed state of the next sub-block when, as the result of the determination, the selected sub-block is determined to be in the erase state.

11. The method of claim 8 , wherein the determining of the erased/programmed state of the selected sub-block uses sub-block information stored in a sub-block information storage included in a control logic, or a verify operation of the selected sub-block.

12. The method of claim 11 , wherein the sub-block information includes information about a sub-block in the erase state or information about a sub-block in the program state, among the sub-blocks included in the selected main block.

13. The method of claim 12 , wherein an erase operation starts to be performed on a sub-block subsequent to the sub-blocks in the erase state when the sub-block information corresponds to information about the sub-blocks in the erase state.

14. The method of claim 12 , wherein an erase operation starts to be performed on a first sub-block according to order of the erase operation, among the sub-blocks in the program state.

15. The method of claim 11 , wherein threshold voltages of memory cells included in the selected sub-block are less than an erase verify voltage or a read voltage when a verify operation of the selected sub-block is used.

16. The method of claim 15 , wherein when the threshold voltages are less than the erase verify voltage or the read voltage, the selected sub-block is determined to be in the erase state, and a next sub-block is selected, and
the erase operation starts to be performed on the selected sub-block when the threshold voltages are greater than the erase verify voltage or the read voltage.

17. The method of claim 16 , wherein the verify operation of the selected sub-block is omitted and the selected sub-block is erased when the selected sub-block is a last sub-block, among the sub-blocks included in the main block.

18. The method of claim 15 , wherein the erase verify voltage is set to a range between −0.5V and +1V, or the read voltage is set to a range between −1V and a positive voltage.

19. The method of claim 18 , wherein the positive voltage is a lowest voltage in a threshold voltage distribution in the program state.

20. The method of claim 8 , wherein the erasing of the sub-blocks after the determining of the erased/programmed state of the selected sub-block comprises:
applying an erase voltage to a source line coupled to the selected sub-block;
applying an erase permission voltage to local word lines coupled to the selected sub-block, and
floating local word lines coupled to unselected sub-blocks except for the selected sub-block.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title