Semiconductor device, memory device, electronic device, or method for driving the semiconductor device

Patent metadata

Field	Value
Publication number	US-9773787-B2
Application number	US-201615338610-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Nov 3, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor are electrically connected to a first terminal of a capacitor, and a control circuit is electrically connected to a second terminal of the capacitor. The control circuit supplies a first potential to the second terminal of the capacitor, in other words, adds a value corresponding to the first potential to the value of first data previously retained in the gate of the second transistor in order to obtain second data. In the second transistor, the second data, specifically, a third potential commensurate with the potential of the gate will be output from a second terminal when a second potential is supplied to a first terminal.

First claim

What is claimed is:

1. A driving method of a semiconductor device,
the semiconductor device comprising:
a first transistor;
a second transistor;
a capacitor; and
a control circuit,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,
wherein a gate of the second transistor is electrically connected to the first terminal of the capacitor,
wherein the control circuit is electrically connected to a second terminal of the capacitor,
wherein first data of m bits is retained in the gate of the second transistor,
wherein m is an integer of 1 or more,
wherein the first data has a value of i,
wherein i is an integer of 0 to 2 m −2, and
wherein j is an integer of 1 to 2 m −1−i,
the driving method comprising the steps of:
supplying a first potential from the control circuit to the second terminal of the capacitor in order to add a value of j that corresponds to the first potential to the value of the first data, so that data retained in the gate of the second transistor is changed from the first data to second data; and
supplying a second potential to a first terminal of the second transistor in order to output a third potential in accordance with a potential of the gate of the second transistor from the second terminal of the second transistor after supplying the first potential, so that the second data is outputted,

wherein, when the second potential is supplied, the second data is retained in the potential of the gate of the second transistor.

2. The driving method according to claim 1 , wherein the third potential is equal to the potential of the gate of the second transistor in supplying the second potential.

3. The semiconductor device configured to use the driving method according to claim 1 ,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises silicon.

4. The semiconductor device configured to use the driving method according to claim 1 ,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises an oxide semiconductor.

5. A memory device comprising:
the semiconductor device according to claim 4 ; and
a driver circuit.

6. An electronic device comprising:
the memory device according to claim 5 ; and
a housing.

7. A driving method of a semiconductor device,
the semiconductor device comprising:
a first transistor;
a second transistor;
a capacitor; and
a control circuit,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the capacitor,
wherein a gate of the second transistor is electrically connected to the first terminal of the capacitor,
wherein the control circuit is electrically connected to a second terminal of the capacitor,
wherein first data of m bits is retained in the gate of the second transistor,
wherein m is an integer of 1 or more,
wherein the first data has a value of i,
wherein i is an integer of 0 to 2 m −1, and
wherein j is an integer of 1 to i,
the driving method comprising the steps of:
supplying a first potential from the control circuit to the second terminal of the capacitor in order to subtract a value of j that corresponds to the first potential from the value of the first data, so that data retained in the gate of the second transistor is changed from the first data to second data; and
supplying a second potential to a first terminal of the second transistor in order to output a third potential in accordance with a potential of the gate of the second transistor from the second terminal of the second transistor after supplying the first potential, so that the second data is outputted,

wherein, when the second potential is supplied, the second data is retained in the potential of the gate of the second transistor.

8. The driving method according to claim 7 , wherein the third potential is equal to the potential of the gate of the second transistor in supplying the second potential.

9. The semiconductor device configured to use the driving method according to claim 7 ,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises silicon.

10. The semiconductor device configured to use the driving method according to claim 7 ,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises an oxide semiconductor.

11. A memory device comprising:
the semiconductor device according to claim 10 ; and
a driver circuit.

12. An electronic device comprising:
the memory device according to claim 11 ; and
a housing.

13. A driving method of a semiconductor device,
the semiconductor device comprising:
a first transistor;
a second transistor; and
a capacitor;

wherein one of a source or a drain of the first transistor is electrically connected to a first terminal of the capacitor,
wherein a gate of the second transistor is electrically connected to the first terminal of the capacitor,
the driving method comprising the steps of:
in writing, supplying a first potential to a gate of the first transistor while supplying a second potential to a second terminal of the capacitor and supplying a third potential to one of a source or a drain of the second transistor; and
in reading, supplying a fourth potential to the one of the source and the drain of the second transistor while supplying a fifth potential to the second terminal of the capacitor and supplying a sixth potential to the gate of the first transistor,

wherein the first potential is higher than the sixth potential, and
wherein the fourth potential is higher than the third potential.

14. The driving method according to claim 13 , wherein the gate of the second transistor is directly connected to the first terminal of the capacitor.

15. The driving method according to claim 13 , wherein the first transistor comprises an oxide semiconductor.

16. The driving method according to claim 13 , wherein the other one of the source and the drain of the first transistor is electrically connected to the other one of the source and the drain of the second transistor.

17. The driving method according to claim 13 , wherein a capacitive coupling coefficient in the semiconductor device is 1.

18. The driving method according to claim 13 ,
wherein the semiconductor device further comprises a control circuit, and
wherein the control circuit is configured to supply the second potential and the fifth potential to the second terminal of the capacitor.

19. The driving method according to claim 13 , wherein the fifth potential is higher than the second potential.

20. The driving method according to claim 13 , wherein the second transistor is off after the writing.

21. The driving method according to claim 13 , wherein the second potential is a reference potential.

22. The driving method according to claim 13 , wherein the second potential is 0 V.

Assignees

• Semiconductor Energy Lab

Inventors

• Matsuzaki Takanori

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title