Broadcast system

Patent metadata

Field	Value
Publication number	US-9716852-B2
Application number	US-201615083716-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Apr 3, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A transmitter device is provided. The transmitter device includes first to m-th memory cells (m is an integer of 2 or more), first to m-th word lines, a first bit line, and an analog circuit. The i-th word line (i is an integer greater than or equal to 1 and less than or equal to m) is electrically connected to the i-th memory cell. The first to m-th memory cells are electrically connected to the analog circuit through the first bit line. The first to m-th memory cells are capable of retaining a potential corresponding to first data. The first to m-th word lines are supplied with a potential corresponding to second data. The analog circuit is capable of performing a multiply-accumulate operation on the first data and the second data, and the first data or the second data includes image data.

First claim

What is claimed is:

1. A transmitter device comprising:
first to m-th memory cells (m is an integer of 2 or more);
first to m-th word lines;
a first bit line;
an analog circuit; and
a second bit line;
wherein the i-th word line (i is an integer greater than or equal to 1 and less than or equal to m) is electrically connected to the i-th memory cell,
wherein the first to m-th memory cells are electrically connected to the analog circuit through the first bit line,
wherein the first to m-th memory cells are capable of retaining a potential corresponding to first data,
wherein the first to m-th word lines are supplied with a potential corresponding to second data,
wherein the analog circuit is capable of performing a multiply-accumulate operation on the first data and the second data,
wherein the first data or the second data includes image data, wherein the i-th memory cell comprises:
a capacitor;
a first transistor; and
a second transistor,
wherein a first terminal of the capacitor is electrically connected to a gate of the first transistor,
wherein a second terminal of the capacitor is electrically connected to the i-th word line,
wherein the second bit line is electrically connected to the gate of the first transistor through the second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to the first bit line, and
wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

2. The transmitter device according to claim 1 , further comprising:
(m+1)-th to (m+m)-th memory cells; and
a third bit line,
wherein the analog circuit comprises a first circuit and a second circuit,
wherein the (m+i)-th memory cell is electrically connected to the i-th word line,
wherein the first circuit is electrically connected to the first bit line,
wherein the second circuit is electrically connected to the (m+1)-th to (m+m)-th memory cells through the third bit line, and
wherein the first circuit is electrically connected to the second circuit through a current mirror circuit.

3. A receiver device comprising:
first to m-th memory cells (m is an integer of 2 or more);
first to m-th word lines;
a first bit line;
an analog circuit; and
a second bit line,
wherein the i-th word line (i is an integer greater than or equal to 1 and less than or equal to m) is electrically connected to the i-th memory cell,
wherein the first to m-th memory cells are electrically connected to the analog circuit through the first bit line,
wherein the first to m-th memory cells are capable of retaining a potential corresponding to first data,
wherein the first to m-th word lines are supplied with a potential corresponding to second data,
wherein the analog circuit is capable of performing a multiply-accumulate operation on the first data and the second data,
wherein the first data or the second data includes image data, wherein the i-th memory cell comprises:
a capacitor;
a first transistor; and
a second transistor,
wherein a first terminal of the capacitor is electrically connected to a gate of the first transistor,
wherein a second terminal of the capacitor is electrically connected to the i-th word line,
wherein the second bit line is electrically connected to the gate of the first transistor through the second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to the first bit line, and
wherein the second transistor comprises a channel formation region comprising an oxide semiconductor.

4. The receiver device according to claim 3 , further comprising:
(m+1)-th to (m+m)-th memory cells; and
a third bit line,
wherein the analog circuit comprises a first circuit and a second circuit,
wherein the (m+i)-th memory cell is electrically connected to the i-th word line,
wherein the first circuit is electrically connected to the first bit line,
wherein the second circuit is electrically connected to the (m+1)-th to (m+m)-th memory cells through the third bit line, and
wherein the first circuit is electrically connected to the second circuit through a current mirror circuit.

5. An electronic device comprising:
the receiver device according to claim 3 ; and
a microphone, a speaker, a display portion, or an operation key.

6. A broadcast system comprising:
a camera;
the transmitter device according to claim 1 ;
a receiver device; and
a display device,
wherein the camera is capable of generating imaging data,
wherein the transmitter device is capable of generating transmission data by compressing the imaging data,
wherein the receiver device is capable of generating video data by decompressing the transmission data,
wherein the display device is capable of displaying the video data after image processing.

7. A broadcast system comprising:
a camera;
the transmitter device;
a receiver device is the receiver device according to claim 3 ; and
a display device,
wherein the camera is capable of generating imaging data,
wherein the transmitter device is capable of generating transmission data by compressing the imaging data,
wherein the receiver device is capable of generating video data by decompressing the transmission data,
wherein the display device is capable of displaying the video data after image processing.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H04N5/44

  Receiver circuitry {for the reception of television signals according to analogue transmission standards} (H04N5/14 takes precedence) · CPC title

• H04N5/38 Primary

  Transmitter circuitry {for the transmission of television signals according to analogue transmission standards} (H04N5/14 takes precedence) · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• H04N5/40

  Modulation circuits · CPC title