Semiconductor device with integrated shunt resistor

US10950509B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10950509-B2
Application numberUS-201916399603-A
CountryUS
Kind codeB2
Filing dateApr 30, 2019
Priority dateMay 9, 2018
Publication dateMar 16, 2021
Grant dateMar 16, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device, comprising: a first chip pad; a power semiconductor chip arranged on the first chip pad and comprising at least a first and a second power electrode; and a clip connected to the first power electrode; wherein an integral part of the clip forms a shunt resistor; and wherein a first contact finger of the shunt resistor is embodied integrally with the clip. 2. The semiconductor device according to claim 1 , wherein a second contact finger of the shunt resistor is embodied integrally with the clip. 3. The semiconductor device according to claim 1 , wherein a distal end of the first contact finger is connected to or forms a first external terminal of the semiconductor device. 4. The semiconductor device according to claim 2 , wherein a distal end of the second contact finger is connected to or forms a second external terminal of the semiconductor device. 5. The semiconductor device according to claim 1 , wherein a distal end of the first contact finger is connected to a first measurement electrode of a semiconductor voltage measuring unit arranged in the semiconductor device. 6. The semiconductor device according to claim 2 , wherein a distal end of the second contact finger is connected to a second measurement electrode of a semiconductor voltage measuring unit arranged in the semiconductor device. 7. The semiconductor device according to claim 5 , wherein the semiconductor voltage measuring unit is embodied monolithically with the power semiconductor chip. 8. The semiconductor device according to claim 5 , wherein the semiconductor voltage measuring unit comprises a semiconductor chip arranged on a main surface of the power semiconductor chip. 9. The semiconductor device according to claim 5 , wherein the semiconductor voltage measuring unit comprises a semiconductor chip arranged laterally next to the power semiconductor chip. 10. The semiconductor device according to claim 1 , wherein a distal end of the clip is connected to or forms an external terminal of the semiconductor device. 11. The semiconductor device according to claim 10 , wherein the external terminal forms a common power terminal of the power semiconductor chip and measurement terminal for measuring a voltage drop across the shunt resistor. 12. The semiconductor device according to claim 1 , further comprising: a second power semiconductor chip arranged on a second chip pad separated from the first chip pad. 13. The semiconductor device according to claim 12 , wherein the clip electrically connects the first power electrode of the first power semiconductor chip to the second chip pad.

Assignees

Inventors

Classifications

  • characterised by changes in properties of the strap connectors during connecting · CPC title

  • Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

  • Bond wires · CPC title

  • characterised by changes in properties of the bond wires during the connecting · CPC title

  • Multiple bond pads having different sizes · CPC title

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Frequently asked questions

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What does patent US10950509B2 cover?
A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W70/466. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).