Wafer scale package for high power devices

Patent metadata

Field	Value
Publication number	US-9559068-B2
Application number	US-201414520270-A
Country	US
Kind code	B2
Filing date	Oct 21, 2014
Priority date	Dec 21, 2005
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages arc mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

First claim

What is claimed is:

1. A semiconductor package comprising:
a conductive layer over an insulation layer;
a semiconductor die mounted on said conductive layer and having an electrode electrically connected to said conductive layer; and
a current sense resistor situated in an opening in said insulation layer, said current sense resistor extending through said insulation layer and electrically connected to said conductive layer, wherein said current sense resistor comprises a plurality of parallel shunts distributed in said insulation layer.

2. The semiconductor package of claim 1 , wherein said current sense resistor fills said opening in said insulation layer.

3. The semiconductor package of claim 1 , wherein said electrode comprises a drain electrode of said semiconductor die.

4. The semiconductor package of claim 1 , wherein said conductive layer comprises a depression and said semiconductor die is situated in said depression.

5. The semiconductor package of claim 1 , wherein said insulation layer comprises a ceramic material.

6. A semiconductor package comprising:
a conductive layer over an insulation layer;
a semiconductor die mounted on said conductive layer and having an electrode electrically connected to said conductive layer; and
a current sense resistor situated in an opening in said insulation layer, said current sense resistor extending through said insulation layer and electrically connected to said conductive layer; and
a plurality of solder stop dimples formed in said conductive layer around said semiconductor die.

7. The semiconductor package of claim 6 , wherein said solder stop dimples have a rounded bottom shape.

8. A semiconductor package comprising:
a conductive layer over an insulation layer;
a semiconductor die mounted on said conductive layer and having an electrode electrically connected to said conductive layer;
a current sense resistor situated in said insulation layer, said current sense resistor extending through said insulation layer and electrically connected to said conductive layer, wherein said current sense resistor comprises a plurality of parallel shunts distributed in said insulation layer; and
at least one via in said insulation layer, wherein said current sense resistor comprises resistive material situated in said at least one via.

9. The semiconductor package of claim 8 , wherein said current sense resistor fills said at least one via in said insulation layer.

10. The semiconductor package of claim 8 , wherein said electrode comprises a drain electrode of said semiconductor die.

11. The semiconductor package of claim 8 , wherein said conductive layer comprises a depression and said semiconductor die is situated in said depression.

12. The semiconductor package of claim 8 , wherein said insulation layer comprises a ceramic material.

13. The semiconductor package of claim 8 , further comprising a plurality of solder stop dimples formed in said conductive layer around said semiconductor die.

14. The semiconductor package of claim 13 , wherein said solder stop dimples have a rounded bottom shape.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Hauenstein Henning M

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title