Multi chip module, method for operating the same and DC/DC converter

Patent metadata

Field	Value
Publication number	US-9711436-B2
Application number	US-201213351072-A
Country	US
Kind code	B2
Filing date	Jan 16, 2012
Priority date	Jan 19, 2011
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A multi chip module having a current sensing circuit and a semiconductor half bridge configuration having two vertically stacked field effect transistor dies that are connected by horizontally extending tap clips at respective opposite sides of their channels, wherein the current sensing circuit is coupled to two checkpoints, at least one being located on one of the tap clips so as to measure a voltage drop over a predetermined portion of the tap clip acting as a shunt resistor for sensing a current that is provided to a switching node of the half bridge configuration.

First claim

The invention claimed is:

1. A multi chip module comprising:
(a) an elongate substrate;
(b) a lead frame having individual contact leads positioned on opposite sides of the substrate and including a group of first contact leads and a group of second contact leads;
(c) a current sensing circuit die mounted on the substrate and having a first current sensing contact pad and a second current sensing contact pad;
(d) a semiconductor half bridge configuration including:
(i) a lower metal tap clip having a bottom surface mounted on the substrate and having a top surface;
(ii) a lower field effect transistor having a bottom surface mounted on the top surface of the lower metal tap clip and having a top surface;
(iii) a central metal tap clip having a bottom surface mounted on the top surface of the lower field effect transistor and having a top surface, the central metal tap clip having a contact portion extending over and contacting the first contact leads;
(iv) an upper field effect transistor having a bottom surface mounted on the top surface of the central metal tap clip and having a top surface; and
(v) a top metal tap clip having a bottom surface mounted on the top surface of the upper field effect transistor, a top surface, and having a contact portion extending over and contacting the second contact leads;

(e) a first bond wire connected between the first current sensing contact ad and a first check point on the to surface of one of the central and top metal tap clips, the first check point being spaced away from the connecting portion of the one central and top metal tap clip; and
(f) a second bond wire connected between the second current sensing contact pad and a second check point near the the connecting portion of the one central and top metal tap clip, the first and second check points being spaced apart to provide a metal resistance between the check points.

2. The multi chip module of claim 1 , in which the first check point is on the central metal tap clip and is connected near to a switching node between a source of the upper field effect transistor and a drain of the lower field effect transistor, and the second check point is on the central metal tap clip and is spaced a distance L from the first check point away from the switching node.

3. The multi chip module of claim 1 , in which the second contact leads are coupled to a drain of the upper field effect transistor, and in which the first check point is on the top metal tap clip and is connected near to the drain of the upper field effect transistor, and the second check point is on the top metal tap clip and is spaced a distance L from the first check point towards the second contact leads.

4. The multi chip module of claim 1 , in which the current sensing circuit die includes gate drive contact pads coupled to gates of the upper and lower field effect transistors.

5. The multi chip module of claim 1 , in which the tap clips are made of copper.

6. The multi chip module of claim 1 , in which the metal tap clips are made of a manganin alloy consisting essentially of 86% copper, 12% manganese and 2% nickel.

7. The multi chip module of claim 6 , in which the lead frame is made of a manganin alloy consisting essentially of 86% copper, 12% manganese and 2% nickel.

Assignees

• Gehrke Dirk
• Texas Instruments Inc

Inventors

• Gehrke Dirk

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title