Semiconductor device

US9490200B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9490200-B2
Application numberUS-201514841643-A
CountryUS
Kind codeB2
Filing dateAug 31, 2015
Priority dateMay 14, 2009
Publication dateNov 8, 2016
Grant dateNov 8, 2016

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper board stacked on the lower board in a board bonding area between the element bonding area and the terminal bonding area, and having an upper conductor layer on the surface thereof; and a switching element connecting member which connects the switching element with the upper conductor layer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power module comprising: a first board assembly; and a second board assembly, wherein the first board assembly includes: a first lower board having a first lower conductor layer formed on a surface thereof; a plurality of first semiconductor devices bonded to the first lower conductor layer in a first element bonding area; a first power supply terminal bonded to the first lower conductor layer in a first terminal bonding area; and a first upper board stacked on the first lower board in a first board bonding area, and having a first upper conductor layer on a surface thereof; the second board assembly includes: a second lower board having a second lower conductor layer formed on a surface thereof; a plurality of second semiconductor devices bonded to the second lower conductor layer in a second element bonding area; an output terminal electrically connected to the first upper conductor layer, and bonded to the second lower conductor layer in a second terminal bonding area; a second upper board stacked on the second lower board in a second board bonding area, and having a second upper conductor layer on a surface thereof; and a second power supply terminal bonded to the second upper conductor layer. 2. The power module according to claim 1 , wherein the first board assembly further comprising a first connecting member which connects the plurality of first semiconductor devices with the first upper conductor layer; the second board assembly further comprising a second connecting member which connects the plurality of second semiconductor devices with the second upper conductor layer. 3. The power module according to claim 1 , further comprising a case which surrounds the first board assembly and the second board assembly, wherein a part of the output terminal is led out of the case. 4. The power module according to claim 3 , wherein a part of the output terminal penetrates the side plate of the case and is led out of the case. 5. The power module according to claim 4 , wherein a part of the output terminal is elongated parallel to the second lower board and is led out of the case. 6. The power module according to claim 1 , wherein the first power supply terminal and second power supply terminal have plate-shaped parts facing each other with a predetermined interval kept therebetween. 7. The power module according to claim 1 , wherein the plurality of first semiconductor devices includes a plurality of first switching elements and a first diode element; the plurality of second semiconductor devices includes a plurality of second switching elements and a second diode element. 8. The power module according to claim 7 , wherein the first board assembly further comprises a first switching element connecting member which connects the plurality of first switching elements with the first upper conductor layer and is elongated parallel to a direction from the first element bonding area to the first terminal bonding area; and a first diode element connecting member which connects the first diode element with the first upper conductor layer, the second board assembly further comprises a second switching element connecting member which connects the plurality of second switching elements with the second upper conductor layer and is elongated parallel to a direction from the second element bonding area to the second terminal bonding area; and a second diode element connecting member which connects the second diode element with the second upper conductor layer. 9. The power module according to claim 7 , wherein the plurality of first switching elements include a plurality of first switching elements arranged spaced from the first diode element at almost the same intervals around the first diode element and in a direction which is different from a direction opposed to one another; the plurality of second switching elements include a plurality of second switching elements arranged spaced from the second diode element at almost the same intervals around the second diode element and in a direction which is different from a direction opposed to one another. 10. The power module according to claim 9 , wherein the first upper conductor layer is formed in a rectangular shape, the plurality of first switching elements are facing one side of the rectangular-shaped first upper conductor layer, and the first switching elements include a pair of first switching elements facing both end portions of the one side of the first upper conductor layer; the second upper conductor layer is formed in a rectangular shape, the plurality of second switching elements are facing one side of the rectangular-shaped second upper conductor layer, and the second switching elements include a pair of second switching elements facing both end portions of the one side of the second upper conductor layer. 11. The power module according to claim 9 , wherein the first diode elements includes a plurality of first diode elements; the first upper conductor layer is formed in a rectangular shape, the plurality of first diode elements are facing one side of the rectangular-shaped first upper conductor layer, and the first diode elements include a pair of first diode elements facing both end portions of the one side of the first upper conductor layer; the second diode elements includes a plurality of second diode elements; the second upper conductor layer is formed in a rectangular shape, the plurality of second diode elements are facing one side of the rectangular-shaped second upper conductor layer, and the second diode elements include a pair of first diode elements facing both end portions of the one side of the second upper conductor layer. 12. The power module according to claim 7 , wherein the first switching elements and second switching elements are elements using a SiC semiconductor.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between laterally-adjacent chips · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • of die-attach connectors · CPC title

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Frequently asked questions

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What does patent US9490200B2 cover?
Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper boa…
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).