Hybrid under-bump metallization component

Patent metadata

Field	Value
Publication number	US-10937735-B2
Application number	US-201816136808-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Sep 20, 2018
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

First claim

What is claimed is:

1. A method, comprising:
depositing solder on an under-bump metallization component, wherein the under-bump metallization component comprises:
one or more solder diffusion layers disposed directly on a plurality of portions of a superconducting layer;
a hermetically sealed superconducting interconnect component; and
one or more intermetallic compound layers disposed directly on respective ones of the one or more solder diffusion layers, wherein the one or more intermetallic compound layers are distinct from the one or more solder diffusion layers;

forming a channel between each of the one or more solder diffusion layers and the plurality of portions of the superconducting layer under respective ones of the one or more solder diffusion layers, wherein the one or more intermetallic compound layers are between the one or more solder diffusion layers and the solder and wherein the solder is in direct contact with the plurality of portions of the superconducting layer; and
filling the channel with the solder to hermetically seal a second superconducting layer, wherein the second superconducting layer is a single layer provided under and spanning each of the plurality of portions of the superconducting layer, wherein the solder is in direct contact with the second superconducting layer and a third superconducting layer within the channel.

2. The method of claim 1 , further comprising mechanically coupling the solder to the under-bump metallization component via the one or more intermetallic compound layers.

3. The method of claim 1 , the hermetically sealed superconducting interconnect is disposed to connect to a superconducting quantum circuit or a flip chip packaged quantum device.

4. The method of claim 1 , further comprising electrically coupling the solder to the under-bump metallization component via the one or more intermetallic compound layers.

5. A method, comprising:
coupling a first under-bump metallization component to a second under-bump metallization component employing an intervening solder between the first under-bump metallization component and the second under-bump metallization component, wherein the first under-bump metallization component is provided on a first side of the intervening solder and the second under-bump metallization component is provided distal to the first under-bump metallization component on a second side of the intervening solder, wherein the first under-bump metallization component and the second under-bump metallization component comprise respective intermetallic compound layers, and wherein the second under-bump metallization component comprises a qubit chip coupled to a superconducting layer and having a first set of solder diffusion layers provided on a first set of respective portions of a second superconducting layer, wherein the first under-bump metallization component comprises a hermetically sealed superconducting interconnect component and a second set of solder diffusion layers provided on a second set of respective portions of a third superconducting layer, wherein the first set of solder diffusion layers, the second set of solder diffusion layers, the first set of respective portions of the second superconducting layer and the second set of respective portions of the third superconducting layer are disposed in the solder, wherein the first set of solder diffusion layers and the second set of solder diffusion layers are covered by the respective intermetallic compound layers and wherein the solder is in provided within a channel and is in direct contact with the second superconducting layer and the second third superconducting layer within the channel; and
forming the hermetically sealed superconducting interconnect component on the first under-bump metallization component based on the coupling.

6. The method of claim 5 , further comprising mechanically coupling the first under-bump metallization component to the second under-bump metallization component.

7. The method of claim 5 , further comprising forming a stud bump on the first under-bump metallization component, wherein the forming the stud bump comprises employing a modified wire bonding process using a wire bonder for the forming the stud bump.

8. The method of claim 5 , further comprising forming a plated pillar on the first under-bump metallization component.

9. The method of claim 5 , wherein the coupling comprises cold welding the first under-bump metallization component to the second under-bump metallization component.

10. The method of claim 5 , wherein the coupling comprises reflow soldering the first under-bump metallization component to the second under-bump metallization component.

Assignees

• IBM

Inventors

• Nah Jae-Woong
• Lewandowski Eric Peter
• Narasgond Adinath Shantinath

Classifications

• H10D64/01304

  characterised by the conductor · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title