VCO-based continuous-time pipelined ADC

Patent metadata

Field	Value
Publication number	US-10924128-B2
Application number	US-201916422579-A
Country	US
Kind code	B2
Filing date	May 24, 2019
Priority date	May 24, 2019
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

First claim

What is claimed is:

1. A pipelined analog-to-digital converter (ADC), comprising:
a continuous-time residue generation front end to quantize an analog input signal, and to generate a first digital signal and an amplified residue signal;
a voltage-controlled-oscillator (VCO) ADC back end to quantize the amplified residue signal, and to generate a second digital signal; and
a digital signal reconstruction filter to filter the first digital signal and the second digital signal, and to generate a final digital signal.

2. The pipelined ADC of claim 1 , wherein the continuous-time residue generation front end comprises:
a quantizer to generate the first digital signal;
a digital-to-analog converter to receive the first digital signal, and to generate a first reconstructed analog signal; and
a delay circuit to delay a first analog input signal to the quantizer, and to generate a first delayed analog input signal, wherein a response of the delay circuit matches a response of a signal path having the quantizer and the digital-to-analog converter.

3. The pipelined ADC of claim 2 , wherein the delay circuit matches magnitude and phase of the signal path.

4. The pipelined ADC of claim 2 , wherein the delay circuit comprises a resistor-capacitor lattice.

5. The pipelined ADC of claim 2 , wherein the delay circuit comprises one or more inductor-capacitor lattices.

6. The pipelined ADC of claim 2 , wherein the continuous-time residue generation front end further comprises:
a node to output a first residue signal representing a difference between the first delayed analog input signal and the first reconstructed analog signal.

7. The pipelined ADC of claim 1 , wherein the continuous-time residue generation front end comprises:
a residue amplifier to amplify a residue signal, and to generate the amplified residue signal.

8. The pipelined ADC of claim 7 , wherein the residue amplifier has a second or higher-order frequency response.

9. The pipelined ADC of claim 1 , wherein the digital signal reconstruction filter comprises:
a first filter to filter the first digital signal;
a second filter to filter the second digital signal; and
a node to combine outputs of the first filter and the second filter, and to generate the final digital signal.

10. The pipelined ADC of claim 9 , wherein:
a ratio of the first filter and the second filter corresponds to: (1) a signal transfer function of a residue amplifier generating the amplified residue signal, and (2) a signal transfer function of the VCO ADC back end.

11. The pipelined ADC of claim 9 , wherein:
a ratio of the first filter and the second filter corresponds to: (1) a signal transfer function of a residue amplifier generating the amplified residue signal, (2) a signal transfer function of the VCO ADC back end, and (3) a noise transfer function of the continuous-time residue generation front end.

12. The pipelined ADC of claim 1 , wherein:
the continuous-time residue generation front end comprises:
a residue amplifier to amplify a residue signal, and to generate the amplified residue signal; and
circuitry to inject a dither at an input of the residue amplifier; and

the pipelined ADC further comprises:
a correlator to cross-correlate the dither and the second digital signal, and to extract: (1) a signal transfer function of a residue amplifier generating the amplified residue signal, and (2) a signal transfer function of the VCO ADC back end.

13. The pipelined ADC of claim 1 , wherein the continuous-time residue generation front end comprises:
a quantizer to generate the first digital signal;
an unsampling block to upsample the first digital signal;
a filter to filter an output of the upsampling block; and
a digital-to-analog converter to receive an output of the filter, and to generate a first reconstructed analog signal.

14. The pipelined ADC of claim 13 , wherein:
the quantizer operates at a first rate;
the digital-to-analog converter operates at a second rate; and
the second rate is the first rate multiplied an upsampling factor of the upsampling block.

15. The pipelined ADC of claim 1 , wherein the VCO ADC back end comprises:
a digital non-linearity correction block to correct non-linearities of the VCO ADC back end.

16. The pipelined ADC of claim 15 , wherein the VCO ADC back end comprises:
a replica VCO ADC to process a known signal; and
a calibration unit to derive coefficients of the digital non-linearity correction block based on a digital output of the replica VCO ADC and the known signal.

17. The pipelined ADC of claim 1 , wherein the VCO ADC back end comprises:
(1) a first voltage-to-current converter to receive the amplified residue signal;
(2) a first signal path having a first ring oscillator to process a positive signal from the first voltage-to-current converter;
(3) a second signal path having a second ring oscillator to process a negative signal from the first voltage-to-current converter; and
(4) a first node to combine outputs of the first signal path and the second signal path.

18. The pipelined ADC of claim 17 , wherein the VCO ADC back end further comprises:
(5) a second voltage-to-current converter to receive the amplified residue signal;
(6) a third signal path having a third ring oscillator to process the positive signal from the second voltage-to-current converter;
(7) a fourth signal path having a fourth ring oscillator to process the negative signal from the second voltage-to-current converter;
(8) a second node to combine outputs of the third signal path and the fourth signal path; and
(9) a third node to combine outputs of the first node and the second node.

19. The pipelined ADC of claim 18 , wherein the VCO ADC back end further comprises:
(10) first circuitry to inject dither having a first polarity to the first signal path and the second signal path; and
(11) second circuitry to inject dither having a second polarity opposite to the first polarity to the third signal path and the fourth signal path.

20. The pipelined ADC of claim 1 , wherein the VCO ADC back end comprises two injection locked ring oscillators.

21. The pipeline ADC of claim 1 , wherein:
the continuous-time residue generation front end is driven by a first clock signal having a first clock frequency; and
the VCO ADC back end is driven by a second clock signal having a second clock frequency that is at least two times the first clock frequency.

22. The pipelined ADC of claim 1 , wherein:
the VCO ADC comprises a decimation filter and an anti-aliasing filter.

23. The pipelined ADC of claim 1 , wherein the VCO ADC back end comprises:
multiple oscillators; and
one or more feedback paths to implement multi-order noise shaping.

24. The pipelined ADC of claim 1 , wherein:
the continuous-time residue generation front end comprises cascaded continuous-time residue generation stages.

25. The pipelined ADC of claim 1 , wherein a number of residue generation stages being used to quantize the analog input signal, and to generate the amplified residue signal, is configurable by a controller.

26. The pipelined ADC of claim 1 , wherein the VCO ADC back end comprises the following in series: a ring oscillator, a phase-to-digital converter, and a differentiator.

27. A method for pipelined analog-to-digital conversion, comprising:
generating, by a continuous-time front end, a firs

Assignees

• Analog Devices International Unlimited Co

Inventors

• Shibata Hajime
• Taylor Gerard E
• Yang Wenhua W

Classifications

• H03M1/64

  with intermediate conversion to phase of sinusoidal {or similar periodical} signals · CPC title

• H03M1/188

  Multi-path, i.e. having a separate analogue/digital converter for each possible range · CPC title

• H03M1/186

  in feedforward mode, i.e. by determining the range to be selected directly from the input signal · CPC title

• H03M1/183

  the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title