Continuous-time oversampling pipeline analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9432045-B2
Application number	US-201414524729-A
Country	US
Kind code	B2
Filing date	Oct 27, 2014
Priority date	Mar 15, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

First claim

I claim:

1. A pipelined analog-to-digital converter (ADC), comprising:
at least one pipeline stage including:
a delay unit to generate an analog input current signal representing a delayed version of an analog input voltage signal;
an encoder circuit including a plurality of encoders to generate a plurality of digital output signals based on the analog input voltage signal and the plurality of interleaved clock signals;
a decoder circuit including a plurality of decoders to generate a plurality of analog output current signals based on the digital output signals and the plurality of interleaved clock signals; and
a subtraction circuit to generate a residue signal based on the analog input current signal and at least one of the plurality of analog output current signals.

2. The pipelined ADC of claim 1 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times the period of the at least one of the plurality of interleaved clock signals.

3. The pipelined ADC of claim 1 , wherein each of the plurality of encoders generates a respective one of the plurality of digital output signals at a different time based on a respective different one of the plurality of interleaved clock signals.

4. The pipelined ADC of claim 1 , wherein each of the plurality of decoders generates a respective one of the plurality of analog output current signals at a different time based on a respective different one of the plurality of interleaved clock signals.

5. The pipelined ADC of claim 1 , wherein the pipeline stage further comprises a clock circuit to generate the plurality of interleaved clock signals from a single clock signal.

6. The pipelined ADC of claim 1 , further comprising an amplification circuit to amplify the residue signal.

7. A method of performing an analog-to-digital conversion, comprising:
delaying, by a delay unit of a pipeline stage, an analog input voltage signal to generate an analog input current signal representing a delayed version of the analog input voltage signal;
encoding, by a plurality of encoders of an encoder circuit of the pipeline stage, a plurality of digital output signals based on the analog input voltage signal and the plurality of interleaved clock signals;
decoding, by a plurality of decoders of a decoder circuit of the pipeline stage, the plurality of digital output signals as a function of the plurality of interleaved clock signals to generate a plurality of analog output current signals; and
generating, by a subtraction circuit of the pipeline stage, a residue signal based on the analog input current signal and at least one of the plurality analog output current signals.

8. The method of claim 7 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times the period of the at least one of the plurality of interleaved clock signals.

9. The method of claim 7 , wherein each of the plurality of encoders generates a respective one of the plurality of digital output signals at a different time based on a respective different one of the plurality of interleaved clock signals.

10. The method of claim 7 , wherein each of the plurality of decoders generates a respective one of the plurality of analog output current signals at a different time based on a respective different one of the plurality of interleaved clock signals.

11. A analog-to-digital converter (ADC), comprising:
means for delaying an analog input voltage signal to generate an analog input current signal representing a delayed version of the analog input voltage signal;
means for encoding the analog input voltage signal to generate a plurality of digital output signals based on the analog input voltage signal and the plurality of interleaved clock signals;
means for decoding the plurality of digital output signals as a function of the plurality of interleaved clock signals to generate a plurality of analog output current signals;
means for subtracting at least one of the plurality of analog output current signals from the analog input current signal to generate a residue signal.

12. The ADC of claim 11 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times the period of the at least one of the plurality of interleaved clock signals.

13. The ADC of claim 11 , wherein the means for encoding generates each of the plurality of digital output signals at a different time based on a respective different one of the plurality of interleaved clock signals.

14. The ADC of claim 11 , wherein the means for decoding generates each of the plurality of analog output current signals at a different time based on a respective different one of the plurality of interleaved clock signals.

15. The method of claim 7 , further comprising generating, by a clock circuit, the plurality of interleaved clock signals from a single clock signal.

16. The method of claim 7 , further comprising amplifying, by an amplification circuit, the residue signal.

17. The ADC of claim 11 , further comprising means for generating the plurality of interleaved clock signals from a single clock signal.

18. The ADC of claim 11 , further comprising means for amplifying the residue signal.

19. The pipelined ADC of claim 1 , wherein the delay unit comprises continuous-time delay blocks.

20. The ADC of claim 11 , wherein the means for delaying the analog signal comprises one or more of the following: transmission line delay block, cascaded LC lattice filters, active-RC delay filter, RC filter, LC filter, and LCR filter.

Assignees

• Analog Devices Global

Inventors

• Shibata Hajime

Classifications

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/44 Primary

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/167

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title