LC lattice delay line for high-speed ADC applications

Patent metadata

Field	Value
Publication number	US-9312840-B2
Application number	US-201414194107-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Feb 28, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.

First claim

What is claimed is:

1. A continuous time (CT) delay line for delaying a differential analog input pair in an analog-to-digital converter comprising a circuit producing a residual signal, the CT delay line comprising:
two or more resonant (LC) lattice structures for generating a delayed differential analog input signal pair, each LC lattice structure comprising two inductive components and two capacitive components, wherein either (1) the two inductive components are cross coupled or (2) the two capacitive components are cross coupled; and
wherein:
the residual signal is produced from the delayed differential analog input signal pair and a filtered version of the differential analog input pair;
the two or more LC lattice structures are cascaded in multiple stages; and
resonant frequencies of the two or more LC lattice structures are placed at adjacent frequencies to provide group delay over a wide-band of frequencies of the differential analog input pair.

2. The CT delay line of claim 1 , wherein:
the inductive components has a inductance L, the capacitive components has a capacitance C, and the an analog-to-digital converter digitizing the differential analog input signal pair has a clock frequency of f CK ;
L and C is determined according to the following, if the delay is matched to 1.5× the clock period of the ADC:

L
=

3
⁢

Z
o

4
⁢

Nf
CK

⁢

⁢
and
⁢

⁢
C

=

3

4
⁢

NZ
o

⁢

f
CK

;

and
N is the number of cascaded lattice structures in the CT delay line.

3. The CT delay line of claim 1 , wherein:
the CT delay line is connected between an input having the differential analog input pair and a summation node having the filtered version of the differential analog input pair;
the differential analog input pair is digitized by a flash analog-to-digital converter (ADC); and
a digital differential output pair of the flash ADC is provided to a digital-to-analog converter DAC to produce the filtered version of the differential analog input pair.

4. The CT delay line of claim 1 , wherein:
the CT delay line is connected between an input having the differential analog input pair and a summation node having the filtered version of the differential analog input pair;
the differential analog input pair is digitized by a delta-sigma analog-to-digital converter (ADC); and
a digital differential output pair of the delta-sigma ADC is provided to a digital-to-analog converter DAC to produce the filtered version of the differential analog input pair.

5. A continuous time (CT) delay line for delaying a differential analog input pair in a circuit producing a residual signal, the CT delay line comprising:
one or more resonant (LC) lattice structures for generating a delayed differential analog input signal pair, each LC lattice structure comprising two inductive components and two capacitive components, wherein either (1) the two inductive components are cross coupled or (2) the two capacitive components are cross coupled; and
wherein:
the residual signal is produced from the delayed differential analog input signal pair and a filtered version of the differential analog input pair;
the inductive components has a inductance L, the capacitive components has a capacitance C, and the an analog-to-digital converter digitizing the differential analog input signal pair has a clock frequency of f CK ;
L and C is determined according to the following, if the delay is matched to 1.5× the clock period of the ADC:

L
=

3
⁢

Z
o

4
⁢

Nf
CK

⁢

⁢
and
⁢

⁢
C

=

3

4
⁢

NZ
o

⁢

f
CK

;

 and
wherein N is the number of cascaded lattice structures in the CT delay line.

6. A plurality of continuous time (CT) delay lines implemented in an integrated circuit chip, wherein each of the CT delay lines comprises:
one or more resonant (LC) lattice structures for delaying a differential analog input, wherein each of the LC lattice structures comprises two inductive components and two capacitive components;
wherein a magnetic flux pattern of the inductive components of the plurality of CT delay lines has a checkered pattern, when a differential alternating current (AC) signal is applied an input of each CT delay line, to reduce coupling between the inductive components in between the plurality of CT delay lines, said checkered pattern alternating a particular flux directionality of adjacent inductive components between (1) X=an inductive component having flux going from the substrate up towards the surface of the integrated circuit chip and (2) O=an inductive component having flux going from the surface of the integrated circuit chip towards the substrate of the integrated circuit chip.

7. The plurality of CT delay lines of claim 6 , wherein:
two of the CT delay lines each comprises two cascaded lattice structures having two inductive components L 1 p , L 1 n in a first lattice structure, and two inductive components L 2 p , and L 2 n in a second lattice structure; and
wherein L 1 p , L 1 n , L 2 p , and L 2 n are spatially arranged as four planar inductors acc

Assignees

• Analog Devices Technology
• Analog Devices Global

Inventors

• Dong Yunzhi
• Li Zhao
• Schreier Richard E
• Shibata Hajime
• Caldwell Trevor Clifford

Classifications

• H03M1/14

  Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03K5/159 Primary

  Applications of delay lines not covered by the preceding subgroups · CPC title