Adaptive digital quantization noise cancellation filters for mash ADCs

Patent metadata

Field	Value
Publication number	US-9768793-B2
Application number	US-201615365867-A
Country	US
Kind code	B2
Filing date	Nov 30, 2016
Priority date	Dec 17, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

For continuous-time multi-stage noise shaping analog-to-digital converters (CT MASH ADCs), quantization noise cancellation often requires accurate estimation of transfer functions, e.g., a noise transfer function of the front end modulator and a signal transfer function of the back end modulator. To provide quantization noise cancellation, digital quantization noise cancellation filters adaptively tracks transfer function variations due to integrator gain errors, flash-to-DAC timing errors, as well as the inter-stage gain and timing errors. Tracking the transfer functions is performed through the direct cross-correlation between the injected maximum length linear feedback shift registers (LFSR) sequence and modulator outputs and then corrects these non-ideal effects by accurately modeling the transfer functions with programmable finite impulse response (PFIR) filters.

First claim

What is claimed is:

1. A method for tracking a transfer function for digital quantization noise cancellation in a multi-stage analog-to-digital converter (ADC), the method comprising:
injecting a dither signal at a quantizer of a front end of the multi-stage ADC, wherein the dither signal is a maximum length linear feedback shift registers sequence;
determining a cross-correlation function of a digital output signal of the multi-stage ADC and the dither signal to determine a transfer function of the multi-stage ADC; and
updating coefficients of a programmable filter for digital quantization noise cancellation based on the cross-correlation function.

2. The method of claim 1 , wherein:
the digital output signal is an output signal of the front end of the multi-stage ADC;
the transfer function is a noise transfer function of the front end; and
the programmable filter filters an output signal of a back end of the multi-stage ADC.

3. The method of claim 1 , wherein:
the digital output signal is an output signal of a back end of the multi-stage ADC;
the transfer function is a signal transfer function of the back end; and
the programmable filter filters an output signal of the front end of the multi-stage ADC.

4. The method of claim 1 , further comprising:
decimating the cross-correlation function to determine decimated coefficients;
wherein updating the coefficients of the programmable filter comprises updating the coefficients based on the decimated coefficients.

5. The method of claim 1 , further comprising:
decimating an output signal of the multi-stage ADC by one or more decimation filters to generate a decimated output signal; and
filtering the decimated output signal by the programmable filter.

6. The method of claim 1 , further comprising:
normalizing the cross-correlation function based on a gain coefficient computed from an estimated signal transfer function of the multi-stage ADC.

7. The method of claim 1 , further comprising:
applying a moving average on a plurality of coefficient sets computed based on the cross-correlation function.

8. A system for tracking a transfer function for digital quantization noise cancellation in a multi-stage analog-to-digital converter (ADC), the system comprising:
a dither block for generating a maximum-length linear feedback shift registers (LFSR) sequence, said dither block coupled to a quantizer of a front end of the multi-stage ADC;
a cross-correlation hardware block receiving a digital output of the multi-stage ADC and the maximum-length LFSR sequence and generating coefficients of a cross-correlation function; and
a digital quantization noise cancellation filter programmable based on the coefficients of the cross-correlation function.

9. The system of claim 8 , wherein the cross-correlation hardware block comprises:
a multiplexer for (1) selecting a value among a plurality of values of the maximum-length sequence and providing the selected value to a correlator during a first time period and (2) selecting another value among a plurality of values of the maximum-length sequence and providing the selected value to the correlator during a second time period.

10. The system of claim 8 , wherein the cross-correlation hardware block comprises:
a multiplexer for (1) selecting an output of a first stage of the multi-stage ADC and providing the selected output of the first stage to a plurality of correlators during a first time period, and (2) selecting an output of a second stage of the multi-stage ADC and providing the selected output of the second stage to the plurality of correlators during a second time period.

11. The system of claim 8 , wherein the maximum-length LFSR sequence is a 2-level dither sequence.

12. The system of claim 8 , wherein the cross-correlation hardware block comprises:
an accumulator for receiving a value of the maximum-length LFSR sequence and the digital output of the multi-stage ADC, wherein a level of the value of the maximum-length LFSR sequence determines whether the digital output is subtracted or added to an accumulated value of the accumulator.

13. The system of claim 8 , further comprising:
a moving average filter for filtering coefficients of the cross-correlation function.

14. The system of claim 13 , wherein the moving average filter has a programmable moving window size.

15. The system of claim 8 , further comprising:
one or more decimation filters for filtering the cross-correlation function.

16. The system of claim 8 , further comprising:
one or more decimation filters for filtering the digital output of the multi-stage ADC and generating a decimated digital output;
wherein the digital quantization noise cancellation filter filters the decimated digital output.

17. The system of claim 8 , further comprising:
a normalization block for normalizing the coefficients of the cross-correlation function to a gain coefficient.

18. The system of claim 8 , further comprising:
a microprocessor on-chip with the multi-stage ADC for controlling the cross-correlation hardware block, reading the coefficients of the cross-correlation function from the cross-correlation hardware block, and programming the digital quantization noise cancellation filter.

19. The system of claim 8 , wherein the multi-stage ADC is a continuous time multi-stage noise shaping ADC.

20. An apparatus comprising:
a plurality of continuous-time analog-to-digital converters (ADCs) in cascade;
means for generating a sequence which approaches an impulse response and injecting the sequence to a quantizer of a first ADC of the plurality of ADCs;
means for computing coefficients of a cross-correlation function between the sequence and a given digital output of one of the plurality of ADCs; and
means for digital quantization noise cancellation which is programmable based on the coefficients of the cross-correlation function.

Assignees

• Analog Devices Global

Inventors

• Meng Qingdong
• Shibata Hajime
• Schreier Richard E
• Mccormick Martin Steven
• Dong Yunzhi
• Silva Jose Barreiro
• Zhao Jialin
• Paterson Donald W
• Yang Wenhua W

Classifications

• H03M1/08 Primary

  of noise {(H03M1/0617 takes precedence)} · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• H03M3/344 Primary

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title