RC lattice delay

Patent metadata

Field	Value
Publication number	US-9762221-B2
Application number	US-201615182430-A
Country	US
Kind code	B2
Filing date	Jun 14, 2016
Priority date	Jun 16, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

First claim

What is claimed is:

1. A continuous time delay line for a residual producing circuit, the continuous time delay line comprising:
a resistor-capacitor (RC) lattice for delaying a differential analog input pair, the RC lattice having first and second resistive components and first and second capacitive components, the first and second resistive components being cross coupled with respect to the first and second capacitive components;
wherein the delayed differential analog input pair and a filtered version of the differential analog input pair are used to generate a residual signal, and parameters of the RC lattice correspond to a phase component of a circuit path producing the filtered version of the differential analog input pair.

2. The continuous time delay line of claim 1 , further comprising:
a first input node and a second input node for receiving the differential analog input pair;
a third resistive component between a first input node and the first resistive component; and
a fourth resistive component between a second input node and the second resistive component.

3. The continuous time delay line of claim 1 , further comprising:
a first output node and a second output node for outputting the delayed differential analog input pair;
a fifth resistive component between a first output node and the first resistive component; and
a sixth resistive component between a second output node and the second resistive component.

4. The continuous time delay line of claim 1 , wherein the RC lattice is a part of a first-order all-pass filter circuit.

5. The continuous time delay line of claim 2 , further comprising:
a first decoupling capacitor coupled to a first node between the third resistive component and the first resistive component; and
a second decoupling capacitor coupled to a second node between the fourth resistive component and the second resistive component.

6. The continuous time delay line of claim 3 , further comprising:
a third decoupling capacitor coupled to a third node between the fifth resistive component and the first resistive component; and
a fourth decoupling capacitor coupled to a fourth node between the sixth resistive component and the second resistive component.

7. The continuous time delay line of claim 1 , wherein the delayed differential analog input pair and the filtered version of the differential analog input pair are coupled to a summation node to generate the residual signal.

8. The continuous time delay line of claim 1 , wherein the filtered version of the differential analog input pair is a signal reconstructed from a digitized version of the differential analog input pair.

9. The continuous time delay line of claim 1 , wherein the differential analog input pair is digitized by an analog-to-digital converter, whose output is provided to a digital-to-analog converter to produce the filtered version of the differential analog input pair.

10. The continuous time delay line of claim 1 , wherein:
the differential analog input pair is an analog output of a first delta-sigma modulator stage;
the differential analog input pair is digitized by an analog-to-digital converter of the first delta-sigma modulator stage, whose output is provided to a digital-to-analog converter to produce the filtered version of the differential analog input pair; and
the residue signal is provided as input to a second delta-sigma modulator stage.

11. A residue producing circuit comprising:
a continuous time delay line to receive an analog input, said continuous time delay line having a resistor-capacitor lattice circuit;
an analog-to-digital converter for converting the analog input to a digital signal;
a digital-to-analog converter for generating a reconstructed analog signal based on the digital signal; and
a node for combining the analog input and the reconstructed analog signal to generate a residue signal;
wherein the continuous time delay line matches a phase component of the analog-to-digital converter and the digital-to-analog converter.

12. The residue producing circuit of claim 11 , wherein the continuous time delay line further comprises decoupling capacitors to add high frequency poles to a transfer function of the continuous time delay line.

13. The residue producing circuit of claim 11 , wherein the continuous time delay line acts as a low pass filter to match a frequency response of the digital-to-analog converter.

14. The residue producing circuit of claim 11 , wherein the residue producing circuit is part of a continuous time pipeline analog-to-digital converter.

15. The residue producing circuit of claim 11 , wherein:
the analog input is an analog output of a first delta-sigma modulator stage;
the analog-to-digital converter is part of the first delta-sigma modulator stage; and
the residue signal is provided as input to a second delta-sigma modulator stage.

16. A method for generating a residue signal, the method comprising:
processing an analog signal by a signal path to generate a filtered analog signal, wherein the processing comprises converting an analog signal into a digital signal, and converting, by a digital-to-analog converter, the digital signal into a filtered analog signal;
generating a delayed analog signal based on the analog signal by a continuous time delay line having a resistor-capacitor (RC) lattice structure, wherein the continuous time delay line matches a phase component of the signal path; and
producing a residual signal based on the delayed analog signal and the filtered analog signal.

17. The method of claim 16 , wherein the continuous time delay line further includes decoupling capacitors coupled to the RC lattice structure to delay the analog signal according to a low-pass filtering response.

18. The method of claim 16 , wherein the RC lattice structure is a part of a first-order all-pass filter circuit.

19. The method of claim 16 , wherein the continuous time delay line has a first frequency response which corresponds to a second frequency response of the digital-to-analog converter.

20. The method of claim 19 , wherein the second frequency response of the digital-to-analog converter comprises a zero-order hold response.

Assignees

• Analog Devices Global

Inventors

• Dong Yunzhi
• Kozlov Victor
• Yang Wenhua W
• Caldwell Trevor Clifford
• Shibata Hajime

Classifications

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03K2005/00254

  using microprocessors · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03K2005/00267

  using D/A or A/D converters · CPC title