Continuous-time analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-9774344-B2
Application number	US-201615240278-A
Country	US
Kind code	B2
Filing date	Aug 18, 2016
Priority date	Mar 15, 2013
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

First claim

What is claimed is:

1. A delaying converter comprising:
an input to receive an analog input voltage signal;
continuous-time circuitry to delay the analog input voltage signal by a predetermined period of time matching a delay of a signal path generating a reconstructed signal of the analog input voltage signal; and
an output to output a continuous current output signal representing a delayed analog input voltage signal.

2. The delaying converter of claim 1 , wherein:
the continuous current output signal and the reconstructed signal are used to generate a residue signal in a continuous-time signal form.

3. The delaying converter of claim 1 , wherein:
the signal path includes an encoder generating a digital output signal based on the analog input voltage signal and a decoder generating the reconstructed signal.

4. The delaying converter of claim 1 , wherein:
the reconstructed signal is a current signal.

5. The delaying converter of claim 1 , wherein the predetermined period of time is based on 1.5 times of a period of a clock signal.

6. The delaying converter of claim 1 , wherein the continuous-time circuitry includes a voltage-to-current converter that generates, based on the analog input voltage signal, the continuous current output signal.

7. The delaying converter of claim 1 , wherein:
the analog input voltage signal comprises positive and negative differential signals; and
the continuous-time circuitry comprises two branches receiving the positive and the negative differential signals respectively.

8. The delaying converter of claim 1 , wherein the continuous-time circuitry comprises:
a first branch comprising a first resistor, a first delay, and a second resistor connected in series; and
a second branch comprising a third resistor, a second delay, and a fourth resistor connected in series.

9. The delaying converter of claim 8 , wherein the first resistor, the first delay, and the second resistor are impedance matched, and the third resistor, the second delay, and the fourth resistor are impedance matched.

10. The delaying converter of claim 8 , wherein the first branch and the second branch are impedance matched.

11. The delaying converter of claim 1 , wherein the continuous-time circuitry include one or more of the following: transmission line delay block, cascaded LC lattice filter, active-RC delay filter, RC filter, LC filter, and LCR filter.

12. The delaying converter of claim 1 , wherein:
the continuous-time circuitry comprise multiple serially connected filters.

13. The delaying converter of claim 1 , wherein:
the continuous-time circuitry comprises impedance matched resistors and a plurality of filters connected in cascade.

14. The delaying converter of claim 13 , wherein the plurality of filters comprises lattice LC filters having inductors and capacitors in criss-crossing configurations.

15. A delaying converter, comprising:
inputs receiving differential analog voltage input signals;
outputs outputting continuous-time current signals; and
first filter and second filter connected in cascade used as delays, wherein the first filter includes first inductors and first capacitors, the second filter includes second inductors and second capacitors, each first inductor is connected in series with a next component in a same branch of the delaying converter, and each first capacitor is connected in series with a next component in another branch of the delaying converter.

16. The delaying converter of claim 15 , further comprising:
a first resistor and a second resistor in series with the inputs respectively; and
a third resistor and a fourth resistor in series with the outputs respectively.

17. The delaying converter of claim 15 , wherein the first filter and the second filter are lattice LC filters.

18. The delaying converter of claim 15 , further comprising one or more further filters connected in cascade with the first and second filters.

19. A method for producing a residue signal, the method comprising:
receiving an analog voltage input signal;
generating a reconstructed signal based on the analog voltage input signal;
delaying the analog voltage input signal to generate a continuous-time current output signal, wherein the delaying matches a delay associated with the generating of the reconstructed signal; and
generating the residue signal based on the continuous-time current output signal and the reconstructed signal.

20. The method of claim 19 , wherein generating the residue signal comprises subtracting the continuous-time current output signal by the reconstructed signal and further reconstructed signals, wherein the reconstructed signal and the further reconstructed signals are scaled down by a factor.

Assignees

• Analog Devices Global

Inventors

• Shibata Hajime

Classifications

• H03M1/167

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03M1/44 Primary

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title