Substrate processing method

US10903081B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10903081-B2
Application numberUS-201715857774-A
CountryUS
Kind codeB2
Filing dateDec 29, 2017
Priority dateDec 11, 2015
Publication dateJan 26, 2021
Grant dateJan 26, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A substrate processing method is provided for performing a plating processing on a substrate having, on a surface thereof, an impurity-doped polysilicon film containing a high concentration of impurities. The substrate processing method includes forming a catalyst layer by supplying, onto the substrate, an alkaline catalyst solution containing a complex of a palladium ion and a monocyclic 5- or 6-membered heterocyclic compound having one or two nitrogen atoms as a heteroatom; and forming a plating layer through electroless plating by supplying a plating liquid onto the substrate after the forming of the catalyst layer.

First claim

Opening claim text (preview).

We claim: 1. A substrate processing method of performing a plating processing on a substrate having, on a surface thereof, an impurity-doped polysilicon film, the substrate processing method comprising: forming a catalyst layer by supplying, onto the substrate, an alkaline catalyst solution containing a complex of a palladium ion and a heterocyclic compound and allowing palladium atoms to be coupled to the impurity-doped polysilicon film without being aggregated; and forming a plating layer through electroless plating by supplying a plating liquid onto the substrate after the forming of the catalyst layer, wherein the impurity-doped polysilicon film contains impurities and a number of atoms as the impurities is equal to or higher than 10 15 /cm 3 of the impurity-doped polysilicon film, and the heterocyclic compound is selected from a group consisting of pyrroline, pyrrole, imidazoline, imidazole, pyrazoline, pyrazole, pyrrolidine, imidazolidine, pyrazolidine and piperidine. 2. The substrate processing method of claim 1 , wherein the substrate further includes a base member and an insulating film formed between the base member and the impurity-doped polysilicon film. 3. The substrate processing method of claim 1 , wherein the heterocyclic compound has a substituent selected from a group consisting of a hydroxyl group, a carboxyl group and a sulfate group. 4. A substrate processing method of performing a plating processing on a substrate having, on a surface thereof, an impurity-doped polysilicon film, the substrate processing method comprising: forming a catalyst layer by supplying, onto the substrate, an alkaline catalyst solution containing a complex of a palladium ion and a heterocyclic compound and allowing palladium atoms to be coupled to the impurity-doped polysilicon film without being aggregated; and forming a plating layer through electroless plating by supplying a plating liquid onto the substrate after the forming of the catalyst layer, wherein the impurity-doped polysilicon film contains impurities and a number of atoms as the impurities is equal to or higher than 10 15 /cm 3 of the impurity-doped polysilicon film, and the heterocyclic compound is selected from a group consisting of pyrroline, imidazoline, pyrazoline, imidazolidine and pyrazolidine.

Assignees

Inventors

Classifications

  • Deposition of metallic or metal-silicide materials · CPC title

  • H10W20/044Primary

    for electroless plating · CPC title

  • for electroplating · CPC title

  • the interconnections being through-semiconductor vias · CPC title

  • comprising use of blind vias during the manufacture · CPC title

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What does patent US10903081B2 cover?
A substrate processing method is provided for performing a plating processing on a substrate having, on a surface thereof, an impurity-doped polysilicon film containing a high concentration of impurities. The substrate processing method includes forming a catalyst layer by supplying, onto the substrate, an alkaline catalyst solution containing a complex of a palladium ion and a monocyclic 5- or…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/044. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 26 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).