Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-10879394-B2
Application number	US-201916503357-A
Country	US
Kind code	B2
Filing date	Jul 3, 2019
Priority date	Jul 31, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A stack is formed on a substrate. The stack includes plural first epitaxial layers and plural second epitaxial layers alternatingly stacked over each other. The first epitaxial layers include sulfur, phosphorous, selenium, arsenic, or combinations thereof. A first etching process is performed on the stack to form a fin. A dielectric layer is formed over the fin. A channel region of the fin is exposed. A second etching process is performed on a first portion of each of the first epitaxial layers in the channel region of the fin using a hydrocarbon etch chemistry. The second etching process etches the first epitaxial layers at a higher etch rate than the second etching process etches the second epitaxial layers. A gate structure is formed around a first portion of each of the second epitaxial layers in the channel region of the fin.

First claim

What is claimed is:

1. A method, comprising:
forming a stack over a substrate, wherein the stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternatingly stacked over each other, and the stack further comprises a plurality of buffer layers respectively between the first and second epitaxial layers;
performing a first etching process on the stack to form a fin;
forming a dielectric layer over the fin;
exposing a channel region of the fin;
performing a second etching process on a first portion of each of the first epitaxial layers in the channel region of the fin using a hydrocarbon etch chemistry, wherein the second etching process etches the first epitaxial layers at a higher etch rate than the second etching process etches the second epitaxial layers; and
forming a gate structure around a first portion of each of the second epitaxial layers in the channel region of the fin.

2. The method of claim 1 , wherein the first epitaxial layers comprise ZnS, AIP, GaP, or combinations thereof, and the second epitaxial layers comprise silicon.

3. The method of claim 1 , wherein the first epitaxial layers comprise ZnS 1-x Se x , GaP 1-x As x , or combinations thereof, where x is greater than 0 and smaller than 1, and the second epitaxial layers comprise SiGe.

4. The method of claim 1 , wherein the first epitaxial layers comprise MgS, AlAs, ZnSe, GaAs, or combinations thereof, and the second epitaxial layers comprise germanium.

5. The method of claim 1 , further comprising:
forming a dummy gate structure across the fin prior to forming the dielectric layer;
forming a spacer extending along sidewalls of the dummy gate structure, wherein source and drain regions of the fin are exposed after forming the spacer;
etching second and third portions of each of the first epitaxial layers respectively in the source and drain regions of the fin; and
epitaxially growing source and drain structures respectively around second portions and third portions of the second epitaxial layers, wherein the second portions of the second epitaxial layers are in the source region of the fin, and the third portions of the second epitaxial layers are in the drain region of the fin.

6. The method of claim 5 , wherein etching the first portion of each of the first epitaxial layers is performed such that a fourth portion of each of the first epitaxial layers remains under the spacer.

7. The method of claim 1 , wherein a lattice constant difference between the first epitaxial layers and the second epitaxial layers is equal to or less than about 5%.

8. A method, comprising:
forming a stack over a substrate, wherein the stack comprises a first buffer layer, a first epitaxial layer, a second buffer layer, and a second epitaxial layer sequentially stacked over one another;
etching the stack to form a fin;
forming a dielectric layer over the fin;
exposing a channel region of the fin;
etching a first portion of each of the first buffer layer and the second buffer layer in the channel region of the fin;
etching a first portion of the first epitaxial layer in the channel region of the fin after etching the first portion of each of the first buffer layer and the second buffer layer in the channel region of the fin; and
forming a gate structure around a first portion of the second epitaxial layer in the channel region of the fin.

9. The method of claim 8 , wherein the first buffer layer comprises ZnS 1-x Se x , where x is greater than or equal to 0 and smaller than or equal to 1.

10. The method of claim 8 , wherein the second buffer layer comprises ZnS 1-x Se x , where x is greater than or equal to 0 and smaller than or equal to 1.

11. The method of claim 8 , wherein the first epitaxial layer comprises silicon, and the second epitaxial layer comprises germanium.

12. The method of claim 8 , wherein the first epitaxial layer comprises germanium, and the second epitaxial layer comprises silicon.

13. The method of claim 8 , further comprising:
forming a dummy gate structure across the fin prior to forming the dielectric layer;
forming a spacer extending along sidewalls of the dummy gate structure, wherein source and drain regions of the fin are exposed after forming the spacer;
etching second and third portions of each of the first buffer layer and the second buffer layer respectively in the source and drain regions of the fin;
etching second and third portions of the first epitaxial layer respectively in the source and drain regions of the fin after etching the second and third portions of each of the first buffer layer and the second buffer layer respectively in the source and drain regions of the fin; and
epitaxially growing source and drain structures respectively around second and third portions of the second epitaxial layer, wherein the second portion of the second epitaxial layer is in the source region of the fin, and the third portion of the second epitaxial layer is in the drain region of the fin.

14. The method of claim 13 , wherein etching the second and third portions of each of the first buffer layer and the second buffer layer is performed such that a fourth portion of each of the first buffer layer and the second buffer layer under the spacer is etched;
wherein etching the second and third portions of the first epitaxial layer is performed such that a fourth portion of the first epitaxial layer under the spacer is etched, wherein a recess is formed under the spacer after etching the second and third portions of the first epitaxial layer;
further comprising:
depositing a dielectric material in the recess; and
etching an excess portion of the dielectric material external to the recess to form an inner spacer.

15. The method of claim 8 , wherein a germanium content of the first epitaxial layer is greater than a germanium content of the second epitaxial layer, and the first buffer layer has a gradually increasing Se content from a bottom of the first buffer layer to a top of the first buffer layer.

16. The method of claim 8 , wherein a germanium content of the first epitaxial layer is greater than a germanium content of the second epitaxial layer, and the second buffer layer has a gradually decreasing Se content from a bottom of the second buffer layer to a top of the second buffer layer.

17. A method, comprising:
forming a semiconductive stack over a substrate, wherein the semiconductive stack comprises a first layer, a first buffer layer on the first layer, a second layer on the first buffer layer, and a second buffer layer on the second layer;
patterning the semiconductive stack to form a fin structure over the substrate;
recessing the first layer and the first and second buffer layers of the fin structure;
forming a dielectric material on a side of the recessed first layer and the recessed first and second buffer layers;
removing the recessed first layer and the recessed first and second buffer layers after forming the dielectric material; and
forming a gate structure to surround the second layer and be in contact with the dielectric material.

18. The method of claim 17 , wherein the first buffer layer comprises metals.

19. The method of claim 17 , wherein the recessed first and second buffer layers are removed prior to the recessed first layer.

20. The method of claim 17 , wherein a lattice constant of the first buffer layer gradually decreases from a bottom of the first buffer layer to a top of the first buffer layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Ling-Yen
• Diaz Carlos H

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title