Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same

Patent metadata

Field	Value
Publication number	US-9431252-B2
Application number	US-201514656847-A
Country	US
Kind code	B2
Filing date	Mar 13, 2015
Priority date	Dec 18, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
forming a first masking layer over a gate stack, a first source/drain region, and a second source/drain region, the first source/drain region and the second source/drain region being on opposing sides of the gate stack;
modifying an etch rate of a portion of the first masking layer such that an etch rate of the first masking layer over the first source/drain region is different than an etch rate of the first masking layer over the second source/drain region;
removing the first masking layer over the first source/drain region, the removing forming a first exposed source/drain region;
doping the first exposed source/drain region with first dopants;
removing the first masking layer;
forming a second masking layer over the gate stack, the first source/drain region, and the second source/drain region;
modifying an etch rate of a portion of the second masking layer such that an etch rate of the second masking layer over the first source/drain region is different than an etch rate of the second masking layer over the second source/drain region;
removing the second masking layer over the second source/drain region, the removing forming a second exposed source/drain region; and
doping the second exposed source/drain region with second dopants.

2. The method of claim 1 , wherein the modifying the etch rate of the portion of the first masking layer comprises implanting germanium into the first masking layer overlying the first exposed source/drain region.

3. The method of claim 2 , wherein the implanting germanium into the first masking layer is performed at an acute angle such that the gate stack and the first masking layer mask the first masking layer over the second source/drain region.

4. The method of claim 3 , wherein the modifying the etch rate of the portion of the second masking layer comprises implanting germanium into the second masking layer overlying the second exposed source/drain region.

5. The method of claim 4 , wherein the implanting germanium into the second masking layer is performed at an acute angle such that the gate stack and the second masking layer masks the second masking layer over the first source/drain region.

6. The method of claim 1 , wherein the modifying the etch rate of the portion of the first masking layer comprises increasing an etch rate of the portion of the first masking layer.

7. The method of claim 1 , wherein the first dopants have a first conductivity type, the second dopants have a second conductivity type, first conductivity type being different than the second conductivity type.

8. The method of claim 1 , wherein the first masking layer and the second masking layer comprises a nitride.

9. A method of forming an integrated circuit, the method comprising:
forming a first masking layer over a gate feature, a first source/drain region, and a second source/drain region, the first source/drain region and the second source/drain region being on opposing sides of the gate feature;
increasing an etch rate of the first masking layer over the first source/drain region such that a first etch rate of the first masking layer over the first source/drain region is different than a second etch rate of the first masking layer over the second source/drain region;
removing the first masking layer over the first source/drain region;
doping the first source/drain region with dopants of a first conductivity type;
forming a second masking layer over the gate feature, the first source/drain region, and the second source/drain region;
increasing an etch rate of the second masking layer over the second source/drain region such that a third etch rate of the second masking layer over the second source/drain region is different than a fourth etch rate of the second masking layer over the first source/drain region;
removing the second masking layer over the second source/drain region; and
doping the second source/drain region with dopants of a second conductivity type.

10. The method of claim 9 , wherein first conductivity type is different than the second conductivity type.

11. The method of claim 9 , wherein the increasing the etch rate of the first masking layer is performed at least in part by implanting ions into only a portion of the first masking layer.

12. The method of claim 11 , wherein the ions comprises germanium ions.

13. The method of claim 11 , wherein the gate feature is on a substrate, and wherein the implanting is performed at an acute angle relative to a major surface of the substrate.

14. The method of claim 9 , wherein the first masking layer and the second masking layer comprises a nitride.

15. A method of forming an integrated circuit, the method comprising:
forming a first masking layer over a gate feature, a first source/drain region, and a second source/drain region, the first source/drain region and the second source/drain region being on opposing sides of the gate feature;
implanting ions in the first masking layer over the first source/drain region, the first masking layer over the second source/drain region being substantially free of the ions;
removing the first masking layer over the first source/drain region, the first masking layer remaining over the second source/drain region;
doping the first source/drain region with dopants having a first conductivity type;
forming a second masking layer over the gate feature, the first source/drain region, and the second source/drain region;
implanting ions in the second masking layer over the second source/drain region, the second masking layer over the first source/drain region being substantially free of the ions;
removing the second masking layer over the second source/drain region, the second masking layer remaining over the first source/drain region; and
doping the second source/drain region with dopants having a second conductivity type.

16. The method of claim 15 , further comprising removing the second masking layer after the doping the second source/drain region.

17. The method of claim 15 , wherein the implanting ions in the first masking layer comprises implanting ions at an angle such that the gate feature and the first masking layer blocks ions from the first masking layer over the second source/drain region.

18. The method of claim 17 , wherein the ions comprises germanium.

19. The method of claim 18 , wherein the first masking layer comprises a nitride layer.

20. The method of claim 15 , further comprising, after the doping the first source/drain region and before forming the second masking layer, removing the first masking layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Zhang Ying

Classifications

• H10P30/40

  into insulating materials · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10D12/211 Primary

  Gated diodes · CPC title

• Y10S438/918

  Special or nonstandard dopant · CPC title