Vertical tunneling finfet

Patent metadata

Field	Value
Publication number	US-2016293756-A1
Application number	US-201514675298-A
Country	US
Kind code	A1
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

First claim

1 . A transistor, comprising:
a silicon substrate; a doped drain region formed in the silicon substrate; an epitaxial source region overlying the doped drain region, the epitaxial source region doped with ions of a polarity opposite that of dopants in the drain region; a fin extending between the epitaxial source region and the doped drain region, the fin doped with ions of a same polarity as the dopants in the drain region; and a multi-layer gate structure abutting opposite sides of the fin, the multi-layer gate structure configured to regulate current flow in the fin in response to an applied voltage.

2 . The transistor of claim 1 wherein the multi-layer gate structure includes an inner gate dielectric layer and an outer metallic layer.

3 . The transistor of claim 1 wherein the epitaxial source region includes two or more of boron, silicon germanium, phosphorous, arsenic, silicon, and silicon carbide.

4 . The transistor of claim 1 wherein a dopant concentration characterizing the epitaxial source region is at least 2-3 times greater than a dopant concentration of the doped drain region.

5 . The transistor of claim 1 wherein a dopant concentration characterizing the doped drain region is 10 times greater than a dopant concentration of the fin.

6 . The transistor of claim 1 wherein the fin has a fin width within a range of 6-12 nm.

7 . The transistor of claim 1 wherein, during operation, a sub-threshold swing value is less than 30 mV/decade.

8 . The transistor of claim 2 wherein, during operation, the transistor turns on in response to a voltage in the range of 0.1-1.0 V applied to the outer metallic layer.

9 . An integrated circuit including the transistor according to claim 1 .

10 . A tunneling FET, comprising:
source, drain, and channel regions arranged substantially perpendicular to a top surface of a semiconductor substrate, the source and drain regions doped with ions of opposite polarity, and the channel region extending between the source and drain regions; a dielectric layer abutting opposite sides of the channel region; and a metal gate in contact with the dielectric layer, the metal gate configured to control a vertical current flow in the channel region, between the source and drain regions, in response to an applied voltage.

11 . The tunneling FET of claim 10 wherein the channel region is in a shape of a fin and the metal gate influences the vertical current flow from two sides of the fin.

12 .- 18 . (canceled)

19 . A device, comprising:
a lightly doped silicon substrate; a fin extending out from a top surface of the substrate, the fin including a drain region and a channel overlying the drain region; a heavily doped source region on top of the fin; isolation regions separating the fin from neighboring fins; a metal gate abutting opposite sides of the fin; an inter-layer dielectric; and front side contacts to the heavily doped source region, the drain region, and the metal gate.

20 . The device of claim 19 wherein the isolation regions include
local isolation regions among a plurality of n-type fins,
local isolation regions among a plurality of p-type fins, and
trench isolation regions separating n-type and p-type devices from one another.

21 . The device of claim 19 , further comprising a gate oxide positioned between the channel and the metal gate.

22 . The device of claim 19 , further comprising silicon nitride sidewall spacers supporting the metal gate.

23 . The device of claim 21 wherein the gate oxide includes one or more of silicon dioxide (SiO 2 ), halfnium oxide (HfO 2 ), and halfnium silicate compounds (HfSiON), HfSiO).

24 . The device of claim 19 wherein the metal gate includes one or more of titanium, titanium nitride, titanium carbide, tungsten, silicon boron carbon nitride, amorphous carbon, and aluminum oxide.

25 . The device of claim 19 wherein the source region is epitaxial.

26 . The device of claim 19 wherein the fin and the drain region have similar polarity, and the source region has a polarity opposite that of the fin and the drain region.

27 . The device of claim 19 wherein the front side contacts have circular cross-sections.

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Zhang John H

Classifications

• H10D84/0195

  the components including vertical IGFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/666

  the conductor further comprising additional layers · CPC title