Method of forming a contact

Patent metadata

Field	Value
Publication number	US-9627258-B1
Application number	US-201615183452-A
Country	US
Kind code	B1
Filing date	Jun 15, 2016
Priority date	Jun 15, 2016
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

First claim

What is claimed is:

1. A method comprising:
forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack;
recessing the first gate stack to form a first trench defined by the spacers, wherein the first trench has a first width, wherein upper portions of the spacers are exposed within the first trench;
forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack;
applying a first implantation to convert the second portion of the first capping layer into a second capping layer;
selectively removing the first portion of the capping layer to expose the upper portions of the spacers while the second capping layer is disposed over the recessed first gate stack; and
selectively removing the upper portions of the spacers to form a second trench, wherein the second trench has a second width that is greater than the first width.

2. The method of claim 1 , wherein the applying of the first implantation includes applying a vertical ion implantation that is perpendicular to a top surface of the substrate.

3. The method of claim 2 , wherein applying the vertical ion implantation includes applying the vertical ion implantation with boron species to the second portion of the first capping layer.

4. The method of claim 1 , wherein the selectively removing of the upper portions of the spacers includes
applying a second implantation to modify the upper portions of the spacers; and
selectively removing the modified upper portions of the spacers to form the second trench.

5. The method of claim 4 , wherein the applying of the second implantation includes applying a tilted ion implantation to the upper portion of the spacer with nitrogen species.

6. The method of claim 4 , further comprising
forming a first hard mask layer in the first trench, prior to the forming of the first capping layer in the first trench; and
forming a second hard mask layer in the second trench, after the selectively removing of the upper portions of the spacers.

7. The method of claim 6 , further comprising:
after the selectively removing of the modified upper portion of spacers to form the second trench, extending the second trench into outside of spacers.

8. The method of claim 7 , further comprising:
forming a second gate stack over the substrate, wherein the dielectric layer separates the second gate stack from the first gate stack;
forming a source/drain feature over the substrate, wherein the source/drain feature is disposed between the first gate stack and the second gate stack, wherein the dielectric layer is disposed over the source/drain feature;
after forming the second hard mask layer, forming a second dielectric layer over the first dielectric layer and the second hard mask layer;
forming a contact hole in the second dielectric layer that extends through the first dielectric layer to expose the source/drain feature; and
filling a conductive layer in the contact hole.

9. The method of claim 8 , wherein forming a contact hole includes:
forming a patterned hard mask over the second dielectric layer, wherein the patterned hard mask has an opening aligned with the source/drain feature; and
etching the second and first dielectric layers through the opening by using the patterned hard mask as an etch mask.

10. A method comprising:
forming a first gate stack over a substrate spacers along sidewalls of the first gate stack, wherein the spacers include a low-k dielectric material;
forming a first dielectric layer over the substrate and on sidewalls of the spacers;
recessing the first gate stack to form a first trench, wherein a portion of the spacers is exposed within the first trench;
forming a first capping layer in the first trench such that a first portion of the first capping layer is disposed over the portion of the spacers and a second portion is disposed over the recessed first gate stack;
applying a first implantation to convert the second portions of the first capping layer into a second capping layer, wherein the second capping layer is different from the first portion of the capping layer;
removing the first portion of the first capping layer to expose the portion of the spacers while the second capping layer is disposed over the recessed first gate stack;
applying a second implantation to modify the portion of the spacers; and
selectively removing the modified portion of the spacers to form second trenches.

11. The method of claim 10 , wherein applying the first implantation includes applying the first implantation with a vertical ion implantation that is perpendicular to a top surface of the substrate.

12. The method of claim 11 , wherein applying the vertical ion implantation includes applying the vertical ion implantation process with boron species to the second portions of the first capping layer.

13. The method of claim 10 , wherein applying the second implantation includes a tilted ion implantation applied to the portion of the spacers with a tilt angle.

14. The method of claim 13 , wherein applying the tilted ion implantation includes applying the tilted ion implantation with nitrogen species to the portion of the spacers.

15. The method of claim 10 , further comprising
forming a first hard mask layer in the first trench prior to forming the first capping layer in the first trench; and
forming a second hard mask layer in the second trench prior to the forming of the first capping layer in the first trench after the selectively removing of the modified portion of the spacers to form second trenches.

16. The method of 15 , further comprising:
forming a source/drain feature over the substrate, wherein first dielectric layer disposed over the source/drain feature;
after forming the hard mask layer in the second trench, forming a second dielectric layer over the first dielectric layer and the hard mask layer;
forming a contact hole in the second dielectric layer that extends through the first dielectric layer and exposes the source/drain feature; and
forming a conductive layer in the contact hole.

17. The method of claim 10 , further comprising:
after the selectively removing of the modified upper portion of spacers to form the second trench, extending the second trench to outside of spacers.

18. A method comprising:
forming a gate structure in a first dielectric layer over a substrate, wherein the gate structure includes a gate stack and opposing sidewall spacers disposed along sidewalls of the gate stack;
removing a first portion of the gate stack to form a first trench extending between the opposing sidewall spacers, wherein a second portion of the gate stack remains after removing the first portion of the gate stack;
removing a portion of the opposing sidewall spacers;
forming a first capping layer over the second portion of the gate stack;
forming a second dielectric layer over the first capping layer;
forming a contact trench through the second dielectric layer; and
forming a contact within the contact trench.

19. The method of claim 18 , further comprising:
forming a second capping layer within the first trench such that a first portion of the second capping layer is disposed over the opposing sidewall spacers and a second portion is disposed over the second portion of the gate stack;
applying a first implanta

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien
• Lin Li-Te
• Chiu Yuan-Hung
• Lin Han-Yu

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/22

  using masks · CPC title