Method and apparatus improving gate oxide reliability by controlling accumulated charge

Patent metadata

Field	Value
Publication number	US-10818796-B2
Application number	US-201715419898-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Jul 11, 2005
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

First claim

What is claimed is:

1. A circuit for processing RF signals, the circuit comprising:
a first RF port;
a second RF port;
a plurality of series MOSFETs coupled together in a stack configuration between the first and second RF ports, the plurality of series MOSFETs, controlled by a first switch control signal, to operate in either a first enable state or a second disable state;
a plurality of shunt MOSFETs coupled together in a stack configuration between the first RF port and ground, the plurality of shunt MOSFETs, controlled by a first shunt control signal, to operate in either a first enable state or a second disable state, wherein at least one of the plurality of shunt MOSFETs comprises a first body and a first accumulated charge sink (ACS) coupled within the first body, and the at least one of the plurality of shunt MOSFETs configured so that, in the second disable state, the at least one of the plurality of shunt MOSFETs is to be disabled and a first negative bias voltage that is substantially negative with respect to ground is to be applied to the first ACS of the at least one of the plurality of shunt MOSFETs; and
a semiconductor-on-insulator substrate, wherein the plurality of series MOSFETs and the plurality of the shunt MOSFETs are included in a semiconductor layer of the semiconductor-on-insulator substrate, wherein the substrate also has an insulating layer, and wherein the circuit is able to pass an RF signal at the first RF port through to the second RF port, with the plurality of series MOSFETs in the first enable state and the plurality of shunt MOSFETs in the second disable state, and the circuit is able to shunt to ground the RF signal at the first RF port, with the plurality of series MOSFETs in the second disable state and the plurality of shunt MOSFETs in the first enable state.

2. The circuit of claim 1 , wherein the at least one of the plurality of shunt MOSFETs further comprises a first source and first drain, and wherein the first negative bias voltage to be applied to the first ACS in the second disable state of the at least one of the plurality of shunt MOSFETs to be substantially negative with respect to the first source, the first drain, and with respect to ground.

3. The circuit of claim 1 or 2 , wherein the semiconductor-on-insulator substrate comprises a thin-film semiconductor layer.

4. The circuit of claim 1 or 2 , wherein the semiconductor layer has a thickness of between approximately 100 angstroms to approximately 2,000 angstroms.

5. The circuit of claim 1 or 2 , wherein the plurality of series MOSFETs and the plurality of shunt MOSFETs have associated sources and drains, and wherein the associated sources and drains of the plurality of series MOSFETs and the plurality of shunt MOSFETs extend through the semiconductor layer to the insulating layer.

6. The circuit of claim 1 , wherein, in the second disable state of the at least one of the plurality of shunt MOSFETs, the first ACS to remove or otherwise control charge that could accumulate in the first body of the at least one of the plurality of shunt MOSFETs.

7. The circuit of claim 6 , wherein the at least one of the plurality of shunt MOSFETs comprises:
an NMOSFET having the first body, a gate, a source, a drain and a gate oxide layer between the gate and the first body, wherein the NMOSFET is to be selectively biased via an ACS bias voltage (V ACS ) to be applied to the first ACS, wherein the V ACS to be substantially negative with respect to ground, the source, and the drain.

8. The circuit of claim 7 , wherein the charge to be removed or otherwise controlled within the first body of the NMOSFET could accumulate in a region proximate the gate oxide.

9. The circuit of claim 7 , wherein the plurality of shunt MOSFETs comprises a plurality of NMOSFETs that includes the at least one of the plurality of shunt MOSFETs that comprises the NMOSFET.

10. The circuit of claim 9 , wherein the plurality of NMOSFETs are respectively coupled to a first accumulated charge sink (ACS) of a plurality of first ACSs, wherein the plurality of first ACSs includes the first ACS coupled within the body of the at least one of the plurality of shunt MOSFETs.

11. The circuit of claim 9 or 10 , wherein the NMOSFET comprises a fully depleted NMOSFET.

12. The circuit of claim 9 or 10 , wherein the NMOSFET comprises a partially depleted NMOSFET.

13. The circuit of claim 1 or 2 , further comprising a load resistor coupled between the second RF port and ground.

14. The circuit of claim 1 or 2 , wherein the circuit comprises an RF switch.

15. The circuit of claim 14 , wherein the RF switch is capable of removing or otherwise controlling charge that could accumulate in the first body of the at least one of the plurality of shunt MOSFETs and of reducing harmonic distortion and/or intermodulation interference of signals to be transmitted through the RF switch with respect to signals to be transmitted through the RF switch without the first negative bias voltage applied.

16. A circuit for processing RF signals, the circuit comprising:
a first RF port;
a second RF port;
a plurality of series NMOSFETs coupled together in a stack configuration between the first and second RF ports, the plurality of series NMOSFETs, controlled by a first switch control signal, to operate in either a first enable state or a second disable state; wherein at least one of the plurality of series NMOSFETs comprises a first NMOSFET having a first body, a gate, a source, a drain, a first accumulated charge sink (ACS) coupled to the first body, and a gate oxide layer between the gate and the first body, wherein the first NMOSFET is to be selectively biased to be in the second disable state via an ACS bias voltage (V ACS ) to be applied to the first ACS, wherein the V ACS to be substantially negative with respect to ground, the first source, and the first drain, and wherein the circuit is able to pass an RF signal at the first RF port through to the second RF port, with the plurality of series NMOSFETs in the first enable state, and the circuit is not able to pass the RF signal at the first RF port through to the second RF port, with the plurality of series NMOSFETs in the second disable state, and a semiconductor-on-insulator substrate, wherein the plurality of series NMOSFETs are included in a semiconductor layer of the semiconductor-on-insulator substrate and wherein the substrate also has an insulating layer.

17. The circuit of claim 16 , further comprising a plurality of shunt MOSFETs coupled together in a stack configuration between the first RF port and the ground, the plurality of shunt MOSFETs controlled by a first shunt control signal to operate in either a first enable state or a second disable state, wherein at least one of the plurality of shunt MOSFETs comprises a second NMOSFET having a second body, a second gate, a second source, a second drain, and a second ACS coupled with the second body and configured so that, in the second disable state, the at least one of the plurality of shunt MOSFETs is to be selectively biased via an ACS bias voltage to be substantially negative with respect to ground, the second source, and the second drain, and to be applied to the second ACS.

18. A circuit for processing RF signals, the circuit comprising:
a first RF port;
and ground;
a plurality of shunt NMOSFETs coupled together in a stack configuration between the first RF port and ground, the plurality of shunt NMOSFETs, controlled by a first shunt control signal, to operate in either a first enable state or a second disable s

Assignees

• Psemi Corp

Inventors

• Stuber Michael A
• Brindle Christopher N
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George P
• Welstand Robert B
• Burgener Mark L
• Dribinsky Alexander
• Kim Tae Youn

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D30/6759

  Silicon-on-sapphire [SOS] substrates · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title