Method and apparatus improving gate oxide reliability by controlling accumulated charge

Patent metadata

Field	Value
Publication number	US-9608619-B2
Application number	US-201313948094-A
Country	US
Kind code	B2
Filing date	Jul 22, 2013
Priority date	Jul 11, 2005
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

First claim

What is claimed is:

1. An accumulated charge control (ACC) NMOSFET (ACC NMOSFET), comprising:
a) an NMOSFET having a floating body, a gate, a source, a drain and a gate oxide layer between the gate and the body, wherein the NMOSFET is selectively biased to operate in an accumulated charge regime, and wherein, but for an accumulated charge control structure, accumulated charge accumulates within the body in a region proximate to the gate oxide when the NMOSFET is biased to operate in the accumulated charge regime; and
b) an accumulated charge control structure comprising an accumulated charge sink (ACS) coupled to the body of the NMOSFET, wherein when the NMOSFET is operated in the accumulated charge regime, an ACS bias voltage (V ACS ) is applied to the ACS to remove or otherwise control the accumulated charge;
wherein the V ACS is sufficiently negative with respect to ground, the source, and the drain to cause removal or control of the accumulated charge.

2. The ACC NMOSFET of claim 1 , wherein the NMOSFET operates in the accumulated charge regime at least when the NMOSFET is biased by means of a gate control voltage (Vg) to operate in an OFF-state (non-conducting state), and wherein the NMSOFET has a threshold voltage (Vth).

3. The ACC NMOSFET of claim 2 , wherein no non-zero DC voltage with respect to ground is applied to either the source or the drain of the NMOSFET.

4. The ACC NMOSFET of claim 2 , wherein no DC voltage with respect to ground is applied to the drain of the NMOSFET.

5. The ACC NMOSFET of claim 2 , wherein the V ACS applied to the ACS comprises a negative voltage, wherein the negative voltage is substantially negative with respect to ground, the source, the drain and the Vth.

6. The ACC NMOSFET of claim 3 , wherein no DC voltage is applied between the source and the drain.

7. The ACC NMOSFET of claim 5 or 6 , wherein the gate control voltage Vg and V ACS are independently controlled.

8. The ACC NMOSFET of claim 1 , wherein removing or otherwise controlling the accumulated charge within the body of the NMOSFET improves linearity of RF signals processed by or coupled to the NMOSFET.

9. The ACC NMOSFET of claim 1 or 2 , wherein the gate and the ACS are coupled together.

10. The ACC NMOSFET of claim 9 , wherein the ACS and the gate are controlled by the gate control voltage Vg.

11. The ACC NMOSFET of claim 1 or 2 , wherein a diode is coupled between the gate and the ACS such that the diode prevents current flow into the body when the NMOSFET is in the ON-state.

12. The ACC NMOSFET of claim 1 or 2 , wherein an electrical coupling means is coupled between the gate and the ACS such that the electrical coupling means prevents current flow into the body when the NMOSFET is ON.

13. The ACC NMOSFET of claim 1 or 2 , wherein, when the NMOSFET is in the OFF state, the V ACS applied to the ACS comprises a negative DC voltage, and wherein the negative DC voltage is substantially more negative than the most negative value of the following: ground, DC voltages applied to the source (Vs) and the drain (Vd), and a threshold voltage (Vth) of the NMOSFET.

14. The ACC NMOSFET of claim 1 or 2 , wherein, when the NMOSFET is in the OFF state, the V ACS applied to the ACS comprises a negative DC voltage, and wherein the negative DC voltage is at least 1 Volt more negative than the most negative value of the following: ground, voltages applied to the source (Vs) and the drain (Vd), and a threshold voltage (Vth) of the NMOSFET.

15. The ACC NMOSFET of claim 2 , wherein when the NMOSFET is biased to operate in the OFF-state (non-conducting state) the gate control voltage Vg is at least 1Volt more negative than the most negative value of the following: ground, DC voltages applied to the source (Vs) and the drain (Vd), and a threshold voltage (Vth) of the NMOSFET.

16. The ACC NMOSFET of claim 2 or 10 , wherein the gate control voltage (Vg) comprises approximately +2.5 Volts thereby turning the NMOSFET ON.

17. The ACC NMOSFET of claim 2 or 10 , wherein the gate control voltage (Vg) comprises approximately −2.5 Volts thereby turning the NMOSFET OFF.

18. The ACC NMOSFET of claim 1 or 2 , wherein the NMOSFET comprises a partially depleted silicon-on-insulator (SOI) NMOSFET.

19. The ACC NMOSFET of claim 1 or 2 , wherein the NMOSFET comprises a fully depleted silicon-on-insulator (SOI) NMOSFET.

20. An accumulated charge control NMOSFET (ACC NMOSFET), comprising:
a) an NMOSFET including a floating body, a gate, a drain, a source, and a gate oxide layer between the gate and the body, wherein the NMOSFET has a threshold voltage (Vth); and
b) an accumulated charge sink (ACS) electrically coupled to the body of the NMOSFET, wherein the NMOSFET operates in an accumulated charge regime when the NMOSFET is biased by means of a gate control voltage (Vg) to operate in an OFF-state (non-conducting state), and wherein, but for the ACS, charge accumulates within the body in a region proximate the gate oxide, and wherein the NMOSFET has no source-to-drain DC voltage applied thereto; and wherein an ACS bias voltage (V ACS ) is applied to the ACS and thereby substantially prevents accumulated charge from accumulating in the body, and wherein V ACS is sufficiently negative with respect to ground, the source, the drain, and Vth to substantially prevent accumulated charge from accumulating in the body; and
c) a silicon-on-insulator substrate having at least a silicon layer and an insulating layer, wherein the NMOSFET and ACS are fabricated in the silicon layer to form the ACC NMOSFET and wherein the NMOSFET body is situated between the source, the drain, the gate oxide, and the insulating layer.

21. The ACC NMOSFET of claim 20 , wherein the source and drain of the NMOSFET extend through an entire thickness of the silicon layer and further down to the insulating layer.

22. The ACC NMOSFET of claim 21 , wherein no non-zero DC voltage with respect to ground is applied to either the source or the drain of the NMOSFET.

23. The ACC NMOSFET of claim 22 , wherein when the NMOSFET is in the OFF state, the V ACS applied to the ACS comprises a negative voltage, wherein the negative voltage is substantially negative with respect to ground, the source, the drain and the Vth.

24. The ACC NMOSFET of claim 22 , wherein no DC voltage is applied between the source and the drain.

25. The ACC NMOSFET of claim 21 , wherein no DC voltage with respect to ground is applied to the drain of the ACC NMOSFET.

26. The ACC NMOSFET of claim 23 or 24 , wherein the gate control voltage Vg and V ACS are independently controlled.

27. The ACC NMOSFET of claim 20 , wherein preventing accumulated charge from accumulating in the body of the NMOSFET improves linearity of RF signals processed by or coupled to the ACC NMOSFET.

28. The ACC NMOSFET of claim 20 or 27 , wherein the NMOSFET is coupled to a second ACC NMOSFET having a second NMOSFET including a second gate, a second source and a second drain, wherein either the second source or second drain of the second NMOSFET is coupled to either the source or the drain of the NMOSFET, thereby conveying applied RF signals to the second NMOSFET, and wherein preventing accumulated charge from accumulating in the body of the OFF-state ACC NMOSFET improves linearity of RF signals coupled to the second ACC NMOSFET.

29. The ACC NMOSFET of claim 28 , w

Assignees

• Peregrine Semiconductor Corp

Inventors

• Stuber Michael A
• Brindle Christopher N
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George P
• Welstand Robert B
• Burgener Mark L
• Dribinsky Alexander
• Kim Tae Youn

Classifications

• H01L29/4908

  Electricity · mapped topic

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H01L29/78615

  Electricity · mapped topic

• H01L29/78657

  Electricity · mapped topic

• H01L29/78654

  Electricity · mapped topic