Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

Patent metadata

Field	Value
Publication number	US-9780775-B2
Application number	US-201514845154-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Jul 11, 2005
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

First claim

What is claimed is:

1. An accumulated charge control N-type MOSFET (ACC N-MOSFET) adapted to control charge accumulated in a body of the N-MOSFET , comprising:
a. a gate, drain, source and a gate oxide layer positioned between the gate and the body, wherein the ACC N-MOSFET is biased to operate in an accumulated charge regime when the ACC N-MOSFET is operated in a non-conducting or near non-conducting state and charge accumulates within the body in a region underneath the gate oxide layer; and
b. an accumulated charge sink (ACS) region operatively connected to the body of the N-MOSFET, wherein, when the ACC N-MOSFET is operated in the accumulated charge regime, a bias voltage (V ACS ) is applied to the ACS region to control or to remove accumulated charge from the ACC N-MOSFET body via the ACS region;

wherein the V ACS is more negative than a lesser of a source bias voltage, a drain bias voltage and ground.

2. The ACC N-MOSFET of claim 1 , wherein the N-MOSFET is fabricated on direct silicon bond substrates by bonding and electrically attaching a film of single-crystal silicon onto a base insulating substrate or on an insulating layer on a base silicon substrate.

3. The ACC N-MOSFET of claim 1 , wherein the gate and the ACS region are coupled together.

4. The ACC N-MOSFET of claim 1 , wherein a diode is coupled between the gate and the ACS such that the diode prevents current flow into the body when the ACC N-MOSFET is in conductive state.

5. The ACC N-MOSFET of claim 1 , wherein the gate and charge sinking terminal are coupled together via a clamping circuit.

6. The ACC N-MOSFET of claim 1 , further comprising a first control signal and a second control signal, wherein:
a. the first control signal is configured to control operating states of the ACC N-MOSFET; and
b. the second control signal is configured to provide the bias voltage (V ACS ).

7. The ACC N-MOSFET of claim 1 , wherein the V ACS is at least one Volt more negative than a lesser of a source bias voltage, a drain bias voltage and ground.

8. A RF switch circuit for switching RF signals, comprising:
a. an RF input port configured to receive an RF signal;
b. an RF output port;
c. a switch transistor grouping having a first node coupled to the RF input port and a second node coupled to the RF output port, wherein the switch transistor grouping is controlled by a first switch control signal; and
d. a shunt transistor grouping having a first node coupled to the RF input port and a second node coupled to ground, wherein the shunt transistor grouping is controlled by a second switch control signal , and wherein the shunt transistor grouping comprises one or more ACC N-MOSFETs of claim 1 ; wherein

when the first switch control signal is enabled, the switch transistor grouping is enabled and the shunt transistor grouping is disabled thereby passing the RF input signal from the RF in-put port to the RF output port, and wherein when the second switch control signal is enabled, the shunt transistor grouping is enabled while the switch transistor grouping is disabled thereby isolating the RF input port from the RF output port.

9. The RF switch circuit of claim 8 , wherein the switch transistor grouping comprises one or more MOSFETs.

10. The RF switch circuit of claim 8 , wherein the switch transistor grouping comprises ACC N-MOSFETs.

11. The RF switch circuit of claim 9 , wherein a number of MOSFETs of the one or more MOSFETs is not equal to a number of ACC N-MOSFETs.

12. The RF switch circuit of claim 8 , wherein the one or more ACC N-MOSFET further comprises drain-to-source resistors; the drain-to-source resistors providing a conduction path between corresponding one or more ACC-N-MOSFETs' drains and sources.

13. The RF switch circuit of claim 12 , wherein each gate of each of the one or more ACC N-MOSFETs is coupled to a gate resistor.

14. The RF switch circuit of claim 13 , wherein each drain-to-source resistor has an impedance substantially equal to an impedance of the gate resistor divided by the number of MOSFETs in the stack.

15. The RF switch circuit of claim 13 , wherein each drain-to-source resistor has an impedance larger than an impedance of the gate resistor divided by the number of MOSFETs in the stack.

16. The RF switch circuit of claim 13 , wherein each drain-to-source resistor has an impedance smaller than an impedance of the gate resistor divided by the number of MOSFETs in the stack.

17. A RF switch circuit for switching RF signals, comprising:
a. a first RF port configured to receive or output a first RF signal;
b. a second RF port configured to receive or output a second RF signal;
c. a RF common port;
d. a first switch transistor grouping having a first node coupled to the first RF port and a second node coupled to the RF common port, wherein the first switch transistor grouping is controlled by a first switch control signal, and wherein the first switch transistor grouping comprises one or more ACC N-MOSFETs of claim 1 ;
e. a second switch transistor grouping having a first node coupled to the second RF port and a second node coupled to the RF common port, wherein the second switch transistor grouping is controlled by a second switch control signal, and wherein the second switch transistor grouping comprises one or more ACC N-MOSFETs of claim 1 ;
wherein, when the first switch control signal is enabled and the second switch control signal is disabled, the first switch grouping is enabled while the second switch grouping is disabled, thereby electrically coupling the first RF port with the RF common port and isolating the second RF port from the RF common port, and wherein when the first switch control signal is disabled and the second switch control signal is enabled, the second switch grouping is enabled while the first switch grouping is disabled, thereby electrically coupling the second RF port with the RF common port and isolating the first RF port from the RF common port.

18. A RF switch circuit for switching RF signals, comprising:
a. a first RF port configured to receive or output a first RF signal;
b. a second RF port configured to receive or output a second RF signal;
c. a RF common port;
d. a first switch transistor grouping having a first node coupled to the first RF port and a second node coupled to the RF common port, wherein the first switch transistor grouping is controlled by a first switch control signal, and wherein the first switch transistor grouping comprises one or more ACC N-MOSFETs of claim 7 ;
e. a second switch transistor grouping having a first node coupled to the second RF port and a second node coupled to the RF common port, wherein the second switch transistor grouping is controlled by a second switch control signal, and wherein the second switch transistor grouping comprises one or more ACC N-MOSFETs of claim 7 ;
wherein, when the first switch control signal is enabled and the second switch control signal is disabled, the first switch grouping is enabled while the second switch grouping is disabled, thereby electrically coupling the first RF port with the RF common port and isolating the second RF port from the RF common port, and wherein when the first switch control signal is disabled and the second switch control signal is enabled, the second switch grouping is enabled while the first switch grouping is disabled, thereby electrically coupling the second RF port with the RF common port and isolating the first RF port from the RF common port.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Brindle Christopher N
• Stuber Michael A
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George
• Burgener Mark L

Classifications

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H01L29/1095

  Electricity · mapped topic

• H01L29/78609

  Electricity · mapped topic