Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Patent metadata

Field	Value
Publication number	US-9755615-B2
Application number	US-201514814404-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Feb 28, 2008
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

First claim

The invention claimed is:

1. A circuit coupled between a first terminal and a second terminal, comprising:
a plurality of stacked elements, the stacked elements proceeding from a first element closest the first terminal and farthest from the second terminal to an n-th element farthest from the first terminal and closest to the second terminal,
a plurality of compensating capacitors associated with the stacked elements,

wherein:
nodes between the elements exhibit parasitic capacitances,
the first terminal is a terminal through which a voltage source is coupled to the circuit;
the stacked elements comprise a first set of elements close to the first terminal and far from the second terminal and a second set of elements far from the first terminal and close to the second terminal,
the compensating capacitors comprise a first set of compensating capacitors associated with the first set of elements and a second set of compensating capacitors associated with the second set of elements,
the first set of compensating capacitors comprises i capacitors (i=1, 2, . . . ), the first capacitor of the first set of capacitors being located in parallel with a first element of the first set of elements, the second capacitor of the first set of capacitors being located in parallel with a series of the first element and a second element of the first set of elements, the third capacitor of the first set of capacitors being located in parallel with a series of the first element, the second element and a third element of the first set of elements and so on, and
the second set of compensating capacitors comprises i corresponding capacitors (i=1, 2, . . . ), the first capacitor of the second set of capacitors being located in parallel with a first element of the second set of elements, the second capacitor of the second set of capacitors being located in parallel with a series of the first element and a second element of the second set of elements, the third capacitor of the second set of capacitors being located in parallel with a series of the first element, the second element and a third element of the second set of elements and so on.

Assignees

• Peregrine Semiconductor Corp

Inventors

• Ranta Tero Tapio
• Bawell Shawn
• Greene Robert W
• Brindle Christopher N
• Englekirk Robert Mark

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H03J3/20

  of single resonant circuit by varying inductance only or capacitance only · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H01G4/002

  Details · CPC title

• H03H11/28 Primary

  Impedance matching networks · CPC title