Semiconductor package with supported stacked die

Patent metadata

Field	Value
Publication number	US-10796975-B2
Application number	US-201616072222-A
Country	US
Kind code	B2
Filing date	Apr 2, 2016
Priority date	Apr 2, 2016
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.

First claim

The claimed invention is:

1. A semiconductor package, comprising:
a substrate having a top substrate surface;
a first integrated circuit provided on the top substrate surface, wherein the first integrated circuit is electrically connected to the substrate;
a first intermediate integrated circuit comprising a first top surface and a first bottom surface, the first bottom surface of the first intermediate integrated circuit on the first integrated circuit, wherein the first intermediate integrated circuit comprises a first bond pad on the first top surface;
a second intermediate integrated circuit comprising a second top surface and a second bottom surface, the second bottom surface on the first top surface such that a first portion of the first top surface is exposed, wherein the second intermediate integrated circuit comprises a second bond pad;
a second integrated circuit comprising a third top surface and a third bottom surface, the second integrated circuit on the second top surface, wherein a first portion of the third bottom surface overhangs the second intermediate integrated circuit; and
an underfill support at least partially between the first portion of the third bottom surface and the first portion of the first top surface, wherein within the underfill support, a wire connects the first bond pad with the second bond pad, wherein the electrical connection between the first integrated circuit and the substrate is external to the underfill support.

2. The semiconductor package of claim 1 , wherein the underfill support comprises one or more filler materials.

3. The semiconductor package of claim 1 , wherein a third bond pad is disposed on a portion of the third top surface overhanging the second intermediate integrated circuit.

4. The semiconductor package of claim 1 , further comprising molding encompassing the first integrated circuit and the second integrated circuit.

5. The semiconductor package of claim 1 , wherein the substrate comprises a bottom substrate surface, wherein one or more package-to-board contacts are disposed on the bottom substrate surface.

6. The semiconductor package of claim 1 , wherein the underfill support is a first underfill support, and a first portion of the second bottom surface overhangs the first intermediate integrated circuit, and wherein the semiconductor package further comprises:
a second underfill support provided in at least a portion of a volume of the first portion of the second bottom surface overhanging the first intermediate integrated circuit.

7. The semiconductor package of claim 6 , wherein the second underfill support is in contact with a portion of the first integrated circuit.

8. The semiconductor package of claim 6 , wherein the top substrate surface comprises a first substrate bond pad, and the wire is a first wire, wherein the top substrate surface comprises a second substrate bond pad, wherein the semiconductor package comprises a second wire connecting the second bond pad to the second substrate bond pad.

9. The semiconductor package of claim 1 , wherein the wire is a first wire, wherein the second intermediate integrated circuit comprises a third bond pad, and wherein the semiconductor package further comprises a second wire connecting the second bond pad to the third bond pad.

10. The semiconductor package of claim 1 , wherein the first intermediate integrated circuit comprises a first side surface, the second integrated circuit comprises a third side surface, and the underfill support comprises a fourth side surface, and wherein the fourth side surface is substantially parallel with the first side surface and the third side surface.

11. The semiconductor package of claim 1 , wherein the second intermediate integrated circuit comprises a second side surface, and the underfill support comprises a fourth side surface, and wherein the fourth side surface is in contact with at least a portion of the second side surface.

12. A method, comprising:
providing a package substrate with a substrate top surface;
attaching a first integrated circuit on the substrate top surface, wherein the first integrated circuit is electrically connected to the package substrate;
attaching a first intermediate integrated circuit comprising a first top surface and a first bottom surface, the first bottom surface of the first intermediate integrated circuit on the first integrated circuit, wherein the first intermediate integrated circuit comprises a first bond pad on the first top surface;
attaching a second intermediate integrated circuit comprising a second top surface and a second bottom surface, the second bottom surface on the first top surface such that a first portion of the first top surface is exposed, wherein the second intermediate integrated circuit comprises a second bond pad;
attaching a second integrated circuit comprising a third top surface and a third bottom surface, the second integrated circuit on the second top surface, wherein an overhang region of a first portion of the third bottom surface overhangs the second intermediate integrated circuit defining a cavity under the second integrated circuit;
providing underfill epoxy in the cavity; and
curing the underfill epoxy to form an underfill support in the cavity, wherein the underfill support is at least partially between the first portion of the third bottom surface and the first portion of the first top surface, and wherein within the underfill support, a wire connects the first bond pad with the second bond pad, wherein the electrical connection between the first integrated circuit and the package substrate is external to the underfill support.

13. The method of claim 12 , further comprising wire bonding, after forming the underfill support, a third bond pad of the second integrated circuit to a first substrate bond pad of the package substrate, wherein the third bond pad is disposed on the overhang region.

14. The method of claim 12 , wherein further comprising wire bonding, prior to providing the underfill epoxy in the cavity, the first bond pad to a first substrate bond pad of the package substrate.

15. The method of claim 12 , wherein providing the underfill epoxy in the cavity further comprises dispensing a predetermined volume of the underfill epoxy adjacent to the cavity.

16. The method of claim 12 , further comprising forming a molding encapsulating the first integrated circuit and the second integrated circuit.

17. The method of claim 16 , wherein forming the molding comprises:
depositing liquid molding epoxy on the substrate top surface; and
applying pressure and heat using a chase to drive cross-linking of the liquid molding epoxy to form the molding.

18. The method of claim 12 , further comprising forming a package-to-board on a substrate bottom surface of the package substrate, the substrate bottom surface opposing the substrate top surface.

19. The method of claim 12 , wherein the cavity is a first cavity, the overhang region is a first overhang region, the underfill support is a first underfill support, and a second overhang region of a first portion of the second bottom surface overhangs the first intermediate integrated circuit defining a second cavity under the second intermediate integrated circuit, and wherein the method further comprises:
forming a second underfill support within the second cavity.

20. The method of claim 19 , further comprising wire bonding, after forming the second underfill support, a third bond pad of the second integrated circuit to a first substrate bond

Assignees

• Intel Corp

Inventors

• Mao Guo

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title