Stacking arrangement for integration of multiple integrated circuits

Patent metadata

Field	Value
Publication number	US-9741644-B2
Application number	US-201514703734-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	May 4, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

First claim

What is claimed is:

1. A stacked integrated circuit system comprising:
a substrate defining a substrate major surface;
a contour support comprising:
a first support frame attached to the substrate major surface and defining a first lateral contact surface substantially orthogonal to the substrate major surface;
a support plate comprising a support plate major surface that is substantially parallel to the substrate major surface, wherein the support plate is on the first support frame, and wherein the support plate comprises at least one of aluminum, anodized aluminum, alumina, aluminum nitride, beryllium oxide, brass, stainless steel, perforated circuit board material, silicon carbide, nickel/iron or alloys of nickel/iron alloy, nickel/iron/molybdenum or alloys of nickel/iron/molybdenum, nickel alloy, iron alloy, or cobalt alloy; and
a second support frame defining a second lateral contact surface substantially orthogonal to the substrate major surface, wherein the second support frame is on the support plate such that the support plate is between the first and second support frames, and wherein the second lateral contact surface is set back from the first lateral contact surface measured in a lateral direction substantially parallel to the substrate major surface;

a first integrated circuit die comprising a first integrated circuit die major surface, wherein the first integrated circuit die major surface is substantially parallel to the substrate major surface and a first side of the first integrated circuit die abuts the first lateral contact surface, such that at least a portion of the first integrated circuit die is between the support plate and the substrate major surface; and
a second integrated circuit die comprising a second integrated circuit die major surface, wherein the second integrated circuit die major surface is substantially parallel to the substrate major surface and a first side of the second integrated circuit die abuts the second lateral contact surface, such that at least a portion of the first integrated circuit die and at least a portion of the support plate are between the second integrated circuit die and the substrate major surface,
wherein the contour support defines a mounting aperture that extends through the contour support in a direction substantially orthogonal to the substrate major surface.

2. The stacked integrated circuit system of claim 1 , wherein the first support frame defines a third lateral contact surface such that the first and third lateral contact surfaces are oriented in different directions, wherein the second support frame defines a fourth lateral contact surface such that the second and fourth lateral contact surfaces are oriented in different directions, wherein the fourth lateral contact surface is set back from the third lateral contact surface measured in a lateral direction substantially parallel to the substrate major surface, wherein a second side of the first integrated circuit die abuts the third lateral contact surface and a second side of the second integrated circuit die abuts the fourth lateral contact surface such that the first and second integrated circuit dies are laterally offset from one another in at least two directions.

3. The stacked integrated circuit system of claim 1 , wherein:
the substrate comprises a plurality of substrate bond pads on the substrate major surface;
the first integrated circuit die comprises a first plurality of integrated circuit bond pads along the first integrated circuit die major surface, wherein the support plate does not cover at least one integrated circuit bond pad of the first plurality of integrated circuit bond pads, and wherein the at least one integrated circuit bond pad is electrically connected to at least one substrate bond pad of the plurality of the substrate bond pads; and
the second integrated circuit die comprises a second plurality of integrated circuit bond pads along the second integrated circuit die major surface, wherein at least one integrated circuit bond pad of the second plurality of integrated circuit bond pads is electrically connected to at least one substrate bond pad of the plurality of the substrate bond pads.

4. The stacked integrated circuit system of claim 1 , wherein the support plate comprises at least one electrically conductive trace that is electrically connected to the first integrated circuit die.

5. The stacked integrated circuit system of claim 1 , wherein the support plate comprises a thermally conductive material.

6. The stacked integrated circuit system of claim 1 , wherein the first support frame, the second support frame, and the support plate are a unitary structure.

7. A stacked integrated circuit system comprising:
a substrate defining a substrate major surface;
a contour support comprising:
a first support frame attached to the substrate major surface and defining a plurality of first lateral contact surfaces substantially orthogonal to the substrate major surface;
a second support frame defining a plurality of second lateral contact surfaces substantially orthogonal to the substrate major surface, wherein the second support frame is on the first support frame, wherein the second support frame is farther from the substrate major surface than the first support frame;

a first plurality of integrated circuit dies attached to the substrate major surface, wherein the first plurality of integrated circuit dies are all within a first plane, wherein each respective integrated circuit die of the first plurality of integrated circuit dies defines a first die major surface substantially parallel to the substrate major surface and has at least one side that abuts at least one lateral contact surface of the plurality of first lateral contact surfaces; and
a second plurality of integrated circuit dies, wherein the second plurality of integrated circuit dies are all within a second plane, wherein each respective integrated circuit die of the second plurality of integrated circuit dies defines a second die major surface substantially parallel to the substrate major surface and has at least one side that abuts at least one lateral contact surface of the plurality of second lateral contact surfaces, and wherein, for each integrated circuit die of the first plurality of integrated circuit dies, at least a portion of the integrated circuit die lies between the substrate major surface and an integrated circuit die of the second plurality of integrated circuit dies.

8. The stacked integrated circuit system of claim 7 , wherein the contour support comprises a thermally conductive material.

9. The stacked integrated circuit system of claim 7 , wherein each of the first plurality of integrated circuit dies abuts at least two lateral contact surfaces of the plurality of first lateral contact surfaces, and wherein each of the second plurality of integrated circuit dies abuts at least two lateral contact surfaces of the plurality of second lateral contact surfaces.

10. The stacked integrated circuit system of claim 7 , wherein the contour support defines a mounting aperture that extends through the contour support in a direction substantially orthogonal to the substrate major surface.

11. The stacked integrated circuit system of claim 7 , wherein:
the substrate comprises a plurality of substrate bond pads on the substrate major surface;
at least one of the first plurality of integrated circuit dies comprises a plurality of first integrated circuit bond pads along the first die major surface, wherein none of the second plurality of integrated circuit dies covers at least one integrated circuit bond pad of the first plurality of integrated circuit bond pads, and where

Assignees

• Honeywell Int Inc

Inventors

• Katti Romney R
• Tucker James L

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W42/287

  materials for magnetic shielding, e.g. ferromagnetic materials · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title