Chip stack packages, methods of fabricating the same, electronic systems including the same and memory cards including the same

Patent metadata

Field	Value
Publication number	US-9293443-B2
Application number	US-201414288305-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	Jan 6, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A chip stack package includes a first chip disposed over a substrate, a second chip disposed over the first chip and having an overhang, and a first supporter attached to a bottom surface of the overhang of the second chip and a sidewall of the first chip. The overhang of the second chip protrudes from the sidewall of the first chip.

First claim

What is claimed is:

1. A chip stack package comprising:
a first chip disposed over a substrate;
a second chip disposed over the first chip and including an overhang, the overhang protruding past a sidewall of the first chip; and
a first supporter attached to a bottom surface of the overhang of the second chip and the sidewall of the first chip,
wherein a thickness of the first supporter increases as it approaches the sidewall of the first chip,
wherein the first supporter extends from the sidewall of the first chip to an end of the overhang, and
wherein the first supporter is disposed on the substantially entire bottom surface of the overhang of the second chip.

2. The chip stack package of claim 1 , wherein the first and second chips longitudinally extend in first and second directions, respectively, so that the first and second chips cross each other.

3. The chip stack package of claim 1 , wherein the sidewall of the first chip is adjacent to the bottom surface of the overhang of the second chip.

4. The chip stack package of claim 2 , wherein the thickness of the first supporter varies according to a distance from the sidewall of the first chip along the second direction.

5. The chip stack package of claim 4 , wherein a thickness of a portion of the first supporter on the sidewall of the first chip is substantially equal to or less than a thickness of the first chip.

6. The chip stack package of claim 1 , wherein the first supporter includes an insulation material.

7. The chip stack package of claim 1 , wherein the first supporter includes an epoxy type material or a silicon-based material.

8. The chip stack package of claim 1 , wherein the first supporter, the first chip, and the second chip have substantially the same coefficient of thermal expansion (CTE).

9. The chip stack package of claim 1 , wherein the overhang of the second chip is a first overhang, further comprising:
a third chip disposed over the second chip and including a second overhang;
a fourth chip disposed over the third chip and including a third overhang;
a second supporter attached to a bottom surface of the third overhang of the fourth chip and a sidewall of the third chip; and
a third supporter attached to a top surface of the second overhang of the third chip and a sidewall of the fourth chip.

10. The chip stack package of claim 9 , wherein the sidewall of the third chip is adjacent to the bottom surface of the third overhang of the fourth chip.

11. The chip stack package of claim 9 , wherein the second supporter longitudinally extends in a first direction and transversely extends in a second direction, and
wherein a thickness of the second supporter varies with a distance from the sidewall of the third chip along the second direction.

12. The chip stack package of claim 9 , wherein a thickness of the second supporter increases as it approaches the sidewall of the third chip from an end of the third overhang of the fourth chip.

13. The chip stack package of claim 12 , wherein a thickness of the second supporter on the sidewall of the third chip is substantially equal to or less than a thickness of the third chip.

14. The chip stack package of claim 9 , wherein the second supporter longitudinally extends in a first direction and transversely extends in a second direction from the sidewall of the third chip to an end of the third overhang of the fourth chip.

15. The chip stack package of claim 9 , further comprising a plurality of chip pads exposed on a first portion of the top surface of the second overhang of the third chip,
wherein the third supporter is attached to a second portion of the top surface of the second overhang of the third chip.

16. The chip stack package of claim 9 , wherein the sidewall of the fourth chip is a sidewall adjacent to the second overhang of the third chip, among sidewalls of the fourth chip.

17. The chip stack package of claim 9 , wherein the third supporter transversely extends in a first direction, and
wherein a thickness of the third supporter increases as it approaches the sidewall of the fourth chip to which the third supporter is attached from an end portion of the second overhang of the third chip.

18. The chip stack package of claim 9 , wherein a thickness of the third supporter on the sidewall of the fourth chip is substantially equal to or less than a thickness of the fourth chip.

Assignees

• Sk Hynix Inc

Inventors

• Nam Jong Hyun

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title