Carrier warpage control for three dimensional integrated circuit (3DIC) stacking

Patent metadata

Field	Value
Publication number	US-10153179-B2
Application number	US-201313779554-A
Country	US
Kind code	B2
Filing date	Feb 27, 2013
Priority date	Aug 24, 2012
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

First claim

What is claimed is:

1. A method of forming a package-on-package (PoP) device, comprising:
temporarily mounting a substrate on a carrier, the substrate having conductive lines and vias;
after mounting the substrate to the carrier, stacking a first die on the substrate, the first die having through vias, wherein stacking the first die on the substrate electrically couples the first die with the conductive lines and the vias of the substrate, wherein the first die comprises:
a first substrate, wherein the through vias of the first die extend from a first surface of the first substrate facing the carrier to a second surface of the first substrate opposing the first surface;
first aluminum pads contacting and extending along the first surface of the first substrate;
second aluminum pads contacting and extending along the second surface of the first substrate, wherein each of the through vias is disposed between and contacts a respective first aluminum pad and a respective second aluminum pad;
a first passivation layer along the first surface of the first substrate, wherein the first passivation layer covers first portions of the first aluminum pads and exposes second portions of the first aluminum pads:
a second passivation layer along the second surface of the first substrate, wherein the second passivation layer covers first portions of the second aluminum pads and exposes second portions of the second aluminum pads;
first conductive pillar proximate the first surface of the first substrate and electrically coupled to the exposed second portions of the first aluminum pads; and
second conductive pillar proximate the second surface of the first substrate and electrically coupled to the exposed second portions of the second aluminum pads, wherein the second conductive pillars are spaced apart from the second passivation layer, wherein stacking the first die comprises bonding the first conductive pillars to the substrate using solder; and

after stacking the first die, stacking a second die on the first die such that the first die is interposed between the second die and the substrate, the second die being electrically coupled to the through vias of the first die such that the first die is electrically interposed between the second die and the substrate, the second die being horizontally offset relative to the first die such that a first portion of the second die is disposed between opposing sidewalls of the first die, and a second portion of the second die is disposed outside the opposing sidewalls of the first die, wherein stacking the second die comprises bonding the second die to the second conductive pillars of the first die using solder, wherein stacking the second die electrically couples the second die with the second conductive pillars of the first die, the second conductive pillars disposed directly below the second die.

2. The method of claim 1 , wherein temporary mounting the substrate comprises temporarily mounting the substrate on the carrier using glue.

3. The method of claim 1 , further comprising performing a pressure anneal on the substrate using a pressure anneal cap prior to the first die and second die being stacked.

4. The method of claim 1 , further comprising flowing an underfill material between the first die and the substrate but not between the first die and the second die.

5. The method of claim 1 , further comprising flowing an underfill material between the first die and the second die but not between the first die and the substrate.

6. The method of claim 1 , further comprising forming a molding material over exposed portions of the substrate, the first die, and the second die.

7. A method of forming a package-on-package (PoP) device, comprising:
temporarily mounting a substrate on a carrier;
bonding connectors of a first die to conductive features of the substrate after mounting the substrate, wherein the first die has a through via, wherein a length of the through via, measured along a first direction perpendicular to a major upper surface of the substrate, is smaller than a height of the first die measured along the first direction between an uppermost surface of the first die facing away from the substrate and a lowermost surface of the first die facing the substrate, wherein bonding connectors of the first die electrically couples the through via to at least one of the conductive features of the substrate;
flowing a first underfill material between the first die and the substrate after bonding connectors of the first die;
stacking a second die on the first die after flowing the first underfill material, the second die horizontally offset relative to the first die, the first die having a first sidewall and a second sidewall opposing the first sidewall, the second die having a third sidewall and a fourth sidewall opposing the third sidewall, wherein after stacking the second die, the third sidewall is laterally between the first sidewall and the second sidewall, and the second sidewall is laterally between the third sidewall and the fourth sidewall, wherein stacking the second die electrically couples the through via of the first die to a connector of the second die;
flowing a second underfill material between the first die and the second die after stacking the second die; and
after flowing the second underfill material, forming a molding material over the substrate, the molding material surrounding the first die, the second die, the first underfill material, and the second underfill material.

8. The method of claim 7 , further comprising forming the substrate from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

9. The method of claim 1 , further comprising removing the carrier after stacking the second die, wherein the first die remains stacked on the substrate after removing the carrier.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Lin Shih Ting
• Yu Chen-Hua

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/073

  of die-attach connectors · CPC title