Fabrication of gate all around device

Patent metadata

Field	Value
Publication number	US-10763337-B2
Application number	US-201916443769-A
Country	US
Kind code	B2
Filing date	Jun 17, 2019
Priority date	Sep 28, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A method of forming a gate-all-around device includes forming a gate electrode layer over a substrate, patterning the gate electrode layer to form a conical frustum-shaped gate electrode, etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode, and after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.

First claim

What is claimed is:

1. A method, comprising:
forming a gate electrode layer over a substrate;
patterning the gate electrode layer to form a conical frustum-shaped gate electrode;
etching the conical frustum-shaped gate electrode to form a through hole extending through top and bottom surfaces of the conical frustum-shaped gate electrode; and
after etching the conical frustum-shaped gate electrode, forming a nanowire in the through hole in the conical frustum-shaped gate electrode.

2. The method of claim 1 , further comprising:
forming a gate dielectric layer to line the through hole in the conical frustum-shaped gate electrode prior to forming the nanowire.

3. The method of claim 2 , wherein forming the gate dielectric layer comprises:
depositing a layer of dielectric material that extends along a bottom surface and sidewalls of the through hole in the conical frustum-shaped gate electrode; and
etching the layer of dielectric material to remove a portion of the layer of dielectric material from the bottom surface of the through hole, wherein another portion of the layer of dielectric material remains extending along the sidewalls of the through hole.

4. The method of claim 1 , wherein forming the nanowire comprises:
depositing a metal-containing material to overfill the through hole in the conical frustum-shaped gate electrode; and
performing a chemical mechanical polish process to remove a portion of the metal-containing material outside the through hole in the conical frustum-shaped gate electrode.

5. The method of claim 4 , wherein the metal-containing material is deposited using a bottom-up deposition process.

6. The method of claim 4 , further comprising:
doping the metal-containing material with an n-type dopant or a p-type dopant during depositing the metal-containing material.

7. The method of claim 6 , wherein doping the metal-containing material is performed such that dopants in an entirety of the metal-containing material are of a same conductivity type.

8. The method of claim 6 , wherein doping the metal-containing material is performed such that top and bottom regions of the metal-containing material have a dopant concentration different from a dopant concentration of a middle region of the metal-containing material.

9. A method, comprising:
forming a gate electrode layer over a conductive layer;
patterning the gate electrode layer into first and second gate electrodes;
patterning the conductive layer into first and second gate pickup regions under the first and second gate electrodes, respectively;
trimming the first and second gate electrodes to respectively expose the first and second gate pickup regions, wherein after trimming the first and second electrodes, the first and second gate electrodes have sloped sidewalls respectively extending from exposed top surfaces of the first and second gate pickup regions at an obtuse angle; and
after trimming the first and second gate electrodes, forming first and second gate contacts respectively over the first and second gate pickup regions.

10. The method of claim 9 , wherein forming the first gate contact is performed such that the first gate contact is in contact with the sloped sidewall of the first gate electrode and the top surface of the first gate pickup region.

11. The method of claim 10 , wherein forming the second gate contact is performed such that the second gate contact is in contact with the top surface of the second gate pickup region and spaced apart from the sloped sidewall of the second gate electrode.

12. The method of claim 9 , wherein forming the first and second gate contacts comprises:
forming a dielectric layer around the first and second gate electrodes;
etching the dielectric layer to form first and second contact holes in the dielectric layer, such that the first and second gate pickup regions are exposed by the first and second contact holes, respectively; and
overfilling the first and second contact holes respectively with the first and second gate contacts using a bottom-up deposition process, such that the first and second gate contacts have spherical structures protruding above the dielectric layer.

13. The method of claim 12 , further comprising:
prior to forming the first and second gate contacts, forming first and second nanowires through the first and second gate electrodes, respectively;
forming a conductive layer across the spherical structures of the first and second gate contacts; and
patterning the conductive layer into first and second source/drain contacts atop the first and second nanowires, respectively.

14. The method of claim 13 , wherein the spherical structures of the first and second gate contacts remain protruding above the dielectric layer after patterning the conductive layer.

15. A method, comprising:
forming in sequence a conductive layer, a dielectric layer and a gate electrode layer over a substrate;
patterning the gate electrode layer to form a gate electrode over the dielectric layer, the gate electrode having a horizontal dimension decreasing as a distance from the dielectric layer increases;
patterning the dielectric layer and the conductive layer to form a patterned dielectric layer under the gate electrode and a source/drain pickup region under the patterned dielectric layer, the source/drain pickup region having a horizontal dimension increasing as a distance from the gate electrode increases;
etching a top surface of the gate electrode until exposing the source/drain pickup region;
after etching the top surface of the gate electrode, forming a gate dielectric layer lining an inner sidewall of the gate electrode; and
forming a nanowire surrounded by the gate dielectric layer.

16. The method of claim 15 , further comprising:
forming a gate contact in contact with a tapered sidewall of the gate electrode.

17. The method of claim 15 , further comprising:
forming a source/drain contact in contact with a tapered sidewall of the source/drain pickup region.

18. The method of claim 15 , wherein forming the nanowire comprises:
depositing a metal-containing material on the source/drain pickup region; and
doping the metal-containing material with an n-type dopant or a p-type dopant during depositing the metal-containing material.

19. The method of claim 18 , further comprising:
planarizing the metal-containing material with the gate dielectric layer.

20. The method of claim 15 , wherein forming the gate dielectric layer comprises:
forming a layer of dielectric material having a vertical portion extending along the inner sidewall of the gate electrode and a horizontal portion extending along the source/drain pickup region; and
removing the horizontal portion of the layer of dielectric material from the source/drain pickup region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yung-Chih
• Liao Yu-Chieh
• Yang Tai-I
• Chen Hsin-Ping

Classifications

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6728

  Vertical TFTs · CPC title