Multi-chip package and method of providing die-to-die interconnects in same

Patent metadata

Field	Value
Publication number	US-10763216-B2
Application number	US-201916677533-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Jun 24, 2009
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

First claim

What is claimed is:

1. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:
providing a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side;
attaching a first die to the first side of the substrate such that a portion of the first die extends beyond an edge of the first side of the substrate; attaching a second die to the first side of the substrate such that a portion of the second die extends beyond the edge of the first side of the substrate;
providing a bridge containing a plurality of electrically or optically conductive features;
positioning the bridge adjacent to the third side of the substrate such that no portion of the substrate is underneath the bridge; and
attaching the bridge to the first die and to the second die, thereby creating a connection between the first die and the second die.

2. The method of claim 1 wherein:
the bridge comprises silicon.

3. The method of claim 2 wherein:
the bridge comprises an active die that constitutes a third die of the multi-chip package; and
the bridge is attached to the first die and to the second die using flip-chip connections.

4. The method of claim 3 further comprising:
attaching the bridge to the substrate using a wirebond.

5. The method of claim 2 wherein:
attaching the bridge comprises using a thermocompression bonding process.

6. The method of claim 2 wherein:
attaching the bridge comprises using a solder reflow process.

7. The method of claim 2 wherein:
providing the substrate comprises forming an aperture through the substrate such that the third side constitutes a portion of an inside perimeter of the substrate.

8. The method of claim 2 wherein:
providing the substrate comprises forming a slot in the substrate such that the third side constitutes a portion of an outside perimeter of the substrate.

9. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:
attaching a first die and a second die to a carrier;
attaching a bridge to the first die and attaching the bridge to the second die;
providing a substrate; and
attaching the first die and the second die to the substrate.

10. The method of claim 9 wherein:
the substrate has a cavity therein; and
attaching the first die and the second die to the substrate comprises locating the bridge within the cavity.

11. The method of claim 9 further comprising:
removing the carrier.

12. The method of claim 9 wherein:
the carrier comprises a heat spreader.

13. The method of claim 9 wherein:
attaching the bridge comprises using a thermocompression bonding process.

14. The method of claim 9 wherein:
the bridge comprises silicon.

15. The method of claim 14 wherein:
the bridge comprises an active die that constitutes a third die of the multi-chip package;
the bridge is attached to the first die and to the second die using flip-chip connections; and
the method further comprises attaching the bridge to the substrate using a wirebond.

16. A method of providing die-to-die interconnects in a multi-chip package, the method comprising:
providing a substrate having a plurality of embedded pads;
forming a cavity in the substrate such that the pads are exposed at a floor of the cavity;

providing a bridge having bumps thereon corresponding to the pads;
placing the bridge in the cavity and aligning the bumps and the pads to each other;
providing a first die and a second die; and
attaching the first die and the second die to the bridge and the substrate.

17. The method of claim 16 wherein:
the bridge comprises silicon.

18. The method of claim 17 wherein:
the bridge comprises an active die that constitutes a third die of the multi-chip package;
the bridge is attached to the first die and to the second die using flip-chip connections; and
the method further comprises attaching the bridge to the substrate using a wirebond.

19. The method of claim 16 wherein:
forming the cavity comprises using one of a laser milling and a plasma etching process.

Assignees

• Intel Corp

Inventors

• Braunisch Henning
• Chiu Chia-Pin
• Aleksov Aleksandar
• Au Hinmeng
• Lotz Stefanie M
• Swan Johanna M
• Sharan Sujit

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title