Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Semiconductor package and manufacturing method
US8941230B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941230-B2 |
| Application number | US-201314010245-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 26, 2013 |
| Priority date | Sep 12, 2012 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor package comprising: a core substrate made of a reinforcement-containing insulating resin, the core substrate including a first surface, a second surface opposite to the first surface, and a first opening penetrating the core substrate from the first surface to the second surface; a metal plate that covers an open end of the first opening on the first surface of the core substrate, the metal plate exposing an outer edge of the first su…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8941230B2 cover?
- A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the out…
- Who is the assignee on this patent?
- Shinko Electric Ind Co
- What technology area does this patent fall under?
- Primary CPC classification H10W70/09. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).