Semiconductor structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9847320-B2
Application number	US-201615172743-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Mar 9, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a first die including a signal pad region and a power pad region; a redistribution layer (RDL) over the first die; a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die; a plurality of second connectors over the RDL and at the side opposite to the first die; a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, wherein a center of the second die is laterally shifted with respect to a center of the first die so as to correspond the signal pad region of the first die to the signal pad region of the second die. An associated method for fabricating the same is also disclosed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first die including a signal pad region and a power pad region;
a redistribution layer (RDL) over the first die;
a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die;
a plurality of second connectors over the RDL and at the side opposite to the first die;
a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, and a center of the second die is laterally shifted with respect to a center of the first die; and
a package substrate bonded to the first die through the second connectors and the RDL;
wherein the power pad region of the first die and the signal pad region of the second die are non-overlapping from a top view perspective.

2. The semiconductor device of claim 1 , wherein the second die includes a high bandwidth memory (HBM) die.

3. The semiconductor device of claim 1 , wherein the signal pad region of the first die is substantially directly above the signal pad region of the second die.

4. The semiconductor device of claim 1 , wherein the signal pad region and the power pad region of the second die are within the edges of the RDL.

5. The semiconductor device of claim 1 , wherein the package substrate is a printed circuit board (PCB).

6. The semiconductor device of claim 1 , further comprising a third die disposed side-by-side to the first die.

7. A semiconductor device, comprising:
a first die including a signal pad region and a power pad region;
a redistribution layer (RDL) over the first die;
a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die;
a plurality of second connectors over the RDL and at the side opposite to the first die;
a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, wherein a center of the second die is laterally shifted with respect to a center of the first die so as to correspond the signal pad region of the first die to the signal pad region of the second die; and
a package substrate bonded to the first die through the second connectors and the RDL;
wherein the package substrate includes a through-hole, and the second die is at least partially disposed in the through hole; and
a center of the through-hole is laterally shifted from a center of the package substrate.

8. The semiconductor device of claim 7 , wherein ball grid array (BGA) balls are disposed over the package substrate at a side opposite to the first die, and the BGA balls surround the through-hole.

9. The semiconductor device of claim 8 , wherein, from a top view perspective, a number of columns of the BGA balls at one side of the through-hole is different from a number of columns of the BGA balls at another side of the through-hole.

10. The semiconductor device of claim 9 , wherein at least one of the BGA balls is directly beneath the first die.

11. A semiconductor device, comprising:
a first die including a signal pad region and a power pad region;
a redistribution layer (RDL) over the first die;
a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die;
a plurality of second connectors over the RDL and at the side opposite to the first die;
a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, and a center of the second die is laterally shifted with respect to a center of the first die; and
a package substrate bonded to the first die through the second connectors and the RDL;
wherein the power pad region of the second die and the signal pad region of the first die are non-overlapping from a top view perspective.

12. A semiconductor device, comprising:
a first die;
a redistribution layer (RDL) over the first die;
a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die;
a plurality of second connectors over the RDL and at the side opposite to the first die;
a second die face-to-face and electrically connected to the first die through the first connectors and the RDL, wherein a center of the second die is laterally shifted with respect to a center of the first die; and
a package substrate bonded to the first die through the second connectors and the RDL, wherein the package substrate includes a recess receiving the second die;
wherein at least a portion of the second connectors extend laterally past edges of the first die, and
the first die has a die size greater than a die size of the second die.

13. The semiconductor device of claim 12 , wherein the second die includes a high bandwidth memory (HBM) die.

14. The semiconductor device of claim 12 , wherein a center of the recess is laterally shifted from a center of the package substrate.

15. The semiconductor device of claim 12 , wherein the package substrate is an interposer.

16. The semiconductor device of claim 12 , wherein the recess extends in a thickness direction through the package substrate.

17. The semiconductor device of claim 12 , further comprising a third die disposed side-by-side to the first die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chien Hsun
• Shen William Wu
• Wu Jiun Yi
• Lee Chien Hsun

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title